The main objectives of Integrated Network Enhanced Telemetry (iNET) are increased data rate and improved spectral efficiency. In this paper we propose the transmission scheme for the physical layer to be coded Quadrature Amplitude Modulation-Orthogonal Frequency Division Multiplexing (QAM OFDM) which enables high data rates and spectrum efficiency. However in high mobility scenarios, the channel is time-varying the receiver design is more challenging. In this paper pilot-assisted channel estimation is used at the receiver, with turbo coding to enhance the performance; while the effect of inter symbol interference (ISI) is mitigated by cyclic prefix. The focus of this paper is to evaluate the performance of OFDM with QAM over an aeronautical channel. The M-QAM with OFDM provides a higher data rate than QPSK hence it is chosen in this paper. The implementation is done using Inverse Fast Fourier Transform (IFFT) and the Fast Fourier Transform (FFT). This paper considers how the performance of Coded QAM OFDM can be enhanced using equalization to compensate for inter symbol interference, and using turbo coding for error correction.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / It has been shown that a multi-symbol detector can improve the detection efficiency of PCM/FM by 3 dB when compared to traditional methods without any change to the transmitted waveform. Although this is a significant breakthrough, further improvements are possible with the addition of Forward Error Correction (FEC). Systematic redundancy can be added by encoding the source data prior to the modulation process, thereby allowing channel errors to be corrected using a decoding circuit. Better detection efficiency translates into additional link margin that can be used to extend the operating range, support higher data throughput, or significantly improve the quality of the received data. This paper investigates the detection efficiency that can be achieved using a multisymbol detector and turbo product coding. The results show that this combination can improve the detection performance by nearly 9 dB relative to conventional PCM/FM systems. The increase in link margin is gained at the expense of a small increase in bandwidth and the additional complexity of the encoding and decoding circuitry.

In wireless communications, the use of multiple antennas at both the transmitter and the receiver is a key technology to enable high data rate transmission without additional bandwidth or transmit power. Multiple-input multiple-output (MIMO) schemes are widely used in many wireless standards, allowing higher throughput using spatial multiplexing techniques. MIMO soft detection poses significant challenges to the MIMO receiver design as the detection complexity increases exponentially with the number of antennas. As the next generation wireless system is pushing for multi-Gbps data rate, there is a great need for high-throughput low-complexity soft-output MIMO detector. The brute-force implementation of the optimal MIMO detection algorithm would consume enormous power and is not feasible for the current technology. We propose a reduced-complexity soft-output MIMO detector architecture based on a trellis-search method. We convert the MIMO detection problem into a shortest path problem. We introduce a path reduction and a path extension algorithm to reduce the search complexity while still maintaining sufficient soft information values for the detection. We avoid the missing counter-hypothesis problem by keeping multiple paths during the trellis search process. The proposed trellis-search algorithm is a data-parallel algorithm and is very suitable for high speed VLSI implementation. Compared with the conventional tree-search based detectors, the proposed trellis-based detector has a significant improvement in terms of detection throughput and area efficiency. The proposed MIMO detector has great potential to be applied for the next generation Gbps wireless systems by achieving very high throughput and good error performance. The soft information generated by the MIMO detector will be processed by a channel decoder, e.g. a low-density parity-check (LDPC) decoder or a Turbo decoder, to recover the original information bits. Channel decoder is another very computational-intensive block in a MIMO receiver SoC (system-on-chip). We will present high-performance LDPC decoder architectures and Turbo decoder architectures to achieve 1+ Gbps data rate. Further, a configurable decoder architecture that can be dynamically reconfigured to support both LDPC codes and Turbo codes is developed to support multiple 3G/4G wireless standards. We will present ASIC and FPGA implementation results of various MIMO detectors, LDPC decoders, and Turbo decoders. We will discuss in details the computational complexity and the throughput performance of these detectors and decoders.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Improving the spectral-efficiency of aeronautical telemetry has been a principal area of research over the last several years due to the increasing demand for more data and the limitation of available spectrum. These efforts have lead to the development of the ARTM Tier 1 SOQPSK and Tier II Multi-h CPM waveforms which improve the spectral efficiency by two and three times, as compared to legacy PCM/FM, while maintaining similar detection efficiency. Now that more spectrally efficient waveform options are becoming available, another challenge is to further increase the detection performance. Better detection efficiency translates into additional link margin that can be used to extend the operating range, support higher data throughput, or significantly improve the quality of the received data. It is well known that Forward Error Correction (FEC) is one means of achieving this objective at the cost of additional overhead and increased receiver complexity. However, as mentioned above, spectral efficiency is also vitally important meaning that the FEC must also have a low amount of overhead. Unfortunately, low overhead and high coding gain are generally conflicting trades, although recent work has shown that Turbo Product Codes (TPC) are a particularly attractive candidate. Computer simulations predict that very impressive gains in detection performance are possible for a relatively small increase in bandwidth. The main drawbacks are the additional complexity of the decoding circuitry and an increase in receive side latency. This paper presents the latest simulation and hardware performance results of PCM/FM, SOQPSK, and Multi-h CPM with TPC.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Most traditional approaches to TT&C have employed waveforms that are neither very power nor bandwidth efficient. A new approach to TT&C waveforms greatly improves these efficiencies. Binary Gaussian Minimum Shift Keying (GMSK) provides a constant envelope bandwidth efficient signal for applications above about 10 Kbps. The constant envelope preserves the spectrum through saturated amplifiers. It provides the best power efficiency when used with turbo coding. For protection against various kinds of burst errors it includes the hybrid interleaving for memory and delay efficiency and packet compatible operations in Time Division Multiple Access (TDMA) environments. Commanding, telemetry, mission data transmission, and tracking are multiplexed in TDMA format.

ABSTRACT SOFT DECODING OF CONVOLUTIONAL PRODUCT CODES ON AN FPGA PLATFORM Sanli, Mustafa M.Sc., Department of Electrical and Electronics Engineering Supervisor: Asst. Prof. Dr. Ali &Ouml / zg&uuml / r YILMAZ September 2005, 79 pages In today&rsquo / s world, high speed and accurate data transmission and storage is necessary in many fields of technology. The noise in the transmission channels and read-write errors occurring in the data storage devices cause data loss or slower data transmission. To solve these problems, the error rate of the received information must be minimized. Error correcting codes are used for detecting and correcting the errors. Turbo coding is an efficient error correction method which is commonly used in various communication systems. In turbo coding, some redundancy is added to the data to be transmitted. The redundant data is used to recover original data from the received data. MAP algorithm is one of the most commonly used soft decision decoding algorithms. In this thesis, hardware implementation of the MAP algorithm is studied. MAP decoding is verified on an FPGA. Virtex2Pro is the platform of choice in this study. The algorithm is written in the VHDL language. A MAP decoder is designed and its operation is verified. Using many MAP decoders concurrently, a convolutional product decoder is implemented as well. Area and speed limitations are discussed.

Abstract High computational complexity constrains truly exhaustive computer searches for good space-time (ST) coded modulations mostly to low constraint length space-time trellis codes (STTrCs). Such codes are primarily devised to achieve maximum transmit diversity gain. Due to their low memory order, optimization based on the design criterion of secondary importance typically results in rather modest coding gains. As another disadvantage of limited freedom, the different low memory order STTrCs are almost exclusively constructed for either slow or fast fading channels. Therefore in practical applications characterized by extremely variable Doppler frequencies, the codes typically fail to demonstrate desired robustness. On the other hand, the main drawback of eventually increased constraint lengths is the prohibitively large decoding complexity, which may increase exponentially if optimal maximum-likelihood decoding (MLD) is applied at the receiver. Therefore, robust ST coded modulation schemes with large equivalent memory orders structured as to allow sub-optimal, low complexity, iterative decoding are needed. To address the aforementioned issues, this thesis proposes parallel concatenated space-time turbo coded modulation (STTuCM). It is among the earliest multiple-input multiple-output (MIMO) coded modulation designs built on the intersection of ST coding and turbo coding. The systematic procedure for building an equivalent recursive STTrC (Rec-STTrC) based on the trellis diagram of an arbitrary non-recursive STTrC is first introduced. The parallel concatenation of punctured constituent Rec-STTrCs designed upon the non-recursive Tarokh et al. STTrCs (Tarokh-STTrCs) is evaluated under different narrow-band frequency flat block fading channels. Combined with novel transceiver designs, the applications for future wide-band code division multiple access (WCDMA) and orthogonal frequency division multiplexing (OFDM) based broadband radio communication systems are considered. The distance spectrum (DS) interpretation of the STTuCM and union bound (UB) performance analysis over slow and fast fading channels reveal the importance of multiplicities in the ST coding design. The modified design criteria for space-time codes (STCs) are introduced that capture the joint effects of error coefficients and multiplicities in the two dimensional DS of a code. Applied to STTuCM, such DS optimization resulted in a new set of constituent codes (CCs) for improved and robust performance over both slow and fast fading channels. A recursive systematic form with a primitive equivalent feedback polynomial is assumed for CCs to assure good convergence in iterative decoding. To justify such assumptions, the iterative decoding convergence analysis based on the Gaussian approximation of the extrinsic information is performed. The DS interpretation, introduced with respect to an arbitrary defined effective Hamming distance (EHD) and effective product distance (EPD), is applicable to the general class of geometrically non-uniform (GNU) CCs. With no constrains on the implemented information interleaving, the STTuCM constructed from newly designed CCs achieves full spatial diversity over quasi-static fading channels, the condition commonly identified as the most restrictive for robust performance over a variety of Doppler spreads. Finally, the impact of bit-wise and symbol-wise information interleaving on the performance of STTuCM is studied.

Στην διπλωματική εργασία γίνεται μελέτη της κωδικοποίησης καναλιού, μελέτη των προβλημάτων που εισάγει το κανάλι, μελετώνται σε βάθος οι turbo κωδικοποιητές και διάφορα κριτήρια τερματισμού, γίνεται μελέτη της επίδρασης της πεπερασμένης ακρίβειας σε turbo συστήματα και προτείνονται αρχιτεκτονικές για την υλοποίηση των turbo αποκωδικοποιητών. / In this thesis we study the problem of channel coding, particularly we study turbo coding and termination criteria. Moreover we study the impact of fix point arithmetic on early stopping iterative turbo decoders and we proposed architectures for the implementation of turbo decoders in hardware.

Orientador: Yuzo Iano / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-08T10:21:08Z (GMT). No. of bitstreams: 1 Arthur_Rangel_D.pdf: 3675976 bytes, checksum: 65350df75e5a9588b1366325ac95ef62 (MD5) Previous issue date: 2007 / Resumo: Esta tese trata da otimização de receptores de TV Digital baseados em OFDM, com avaliação de desempenho em redes de retransmissão em freqüência única (SFN . Single Frequency Networks) regionais. Tal ambiente facilita a distribuição de canais, porém possui características que dificultam o trabalho do receptor. São tratados, inicialmente, de projetos de filtros canceladores de elos de realimentação em estações retransmissoras, que ocorrem quando a antena de transmissão interfere na antena de recepção. Um novo filtro, baseado em técnicas que utilizam informação temporal é proposto. Novas propostas são feitas para as partes de sincronismo, estimação e equalização de canal, e codificação/decodificação. Uma técnica, vinda da teoria de reconhecimento de padrões, é aplicada para diminuição da complexidade no processo de sincronismo temporal. Um sistema de estimação de canal 2D e equalização adaptativa, usando o LMS (Least Mean Square), é comparado com técnicas clássicas da literatura, e um ganho significativo é encontrado. Como novo esquema de codificação e decodificação é proposto um esquema iterativo, baseado em códigos turbo, com número reduzido de iterações. Tal código melhora o desempenho do sistema em relação ao uso combinado dos decodificadores Viterbi e Reed Solomon. Todas as propostas são combinadas para se avaliar o desempenho do receptor diante de condições típicas de SFN e multicaminhos típicos em recepção de TV do Brasil / Abstract: This thesis deals with the optimization of Digital TV receivers based on OFDM, with performance evaluation in regional single frequency networks (SFN). Such environment facilitates the channel distribution, however its characteristics degrade the receiver operation. Initially, projects of loop canceller filters in relay stations are treated, and they are necessary when the transmission antenna causes interference on reception antenna. A new filter, based on time information is proposed. New proposals are made for the synchronism, channel estimation and equalization, and coding/decoding. One technique, coming from the pattern recognition theory, is applied for complexity reduction in the process of time synchronism. A 2D channel estimation system and adaptive equalization, using LMS (Least Mean Square), is compared to classical techniques in the literature, and a significant gain is achieved. As a new coding and decoding scheme, an iterative system based on turbo codes is used with reduced number of iterations. Such code improves the system performance when compared to the Viterbi and Reed Solomon concatenated decoders. The proposals are combined and the performance of the proposed receiver is evaluated on typical conditions of SFN and on typical multipaths for TV reception in Brazil / Doutorado / Telecomunicações e Telemática / Doutor em Engenharia Elétrica

To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for flexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.