<p>Today electronics becomes more and more complex and to keep low costs and power consumption, both digital and analog parts are implemented on the same chip. The degree of automization for the digital parts have increased fast and is high, but for the analog parts this has not come through. This have created a big gap between the degrees of automization for the two parts and makes the analog parts the bottleneck in electronics develop. </p><p>Research is ongoing at Electronics systems group at Linköping University target the increase of design automization for analog circuits. An optimizationbased approach for device sizing is developed and for this a good optimization method is needed which can find good solutions and meet the specification parameters. </p><p>This report contains an evaluation of the optimization method Simulated Annealing. Many test runs have been made to find out good control parameters, both for Adaptiv Simulated Annealing (ASA) and a standard Simulated Annealing method. The result is discussed and all the data is in the enclosures. A popular science and mathematical description is given for Simulated Annealing as well.</p>

The aim and goal of this work has been to design and implement a voltage reference network for a 12-bit PSAADC, Parallell Successive Analog to Digital Converter. A chip containing the design has been sent away for fabrication. Because of the long processing time, no measurement data are presented. The main specifications for the voltage reference generator is to generate stable reference voltages with low noise and a good PSRR. Efforts has also been made to minimize the power consumption.

Today electronics becomes more and more complex and to keep low costs and power consumption, both digital and analog parts are implemented on the same chip. The degree of automization for the digital parts have increased fast and is high, but for the analog parts this has not come through. This have created a big gap between the degrees of automization for the two parts and makes the analog parts the bottleneck in electronics develop. Research is ongoing at Electronics systems group at Linköping University target the increase of design automization for analog circuits. An optimizationbased approach for device sizing is developed and for this a good optimization method is needed which can find good solutions and meet the specification parameters. This report contains an evaluation of the optimization method Simulated Annealing. Many test runs have been made to find out good control parameters, both for Adaptiv Simulated Annealing (ASA) and a standard Simulated Annealing method. The result is discussed and all the data is in the enclosures. A popular science and mathematical description is given for Simulated Annealing as well.

<p>The aim and goal of this work has been to design and implement a voltage reference network for a 12-bit PSAADC, Parallell Successive Analog to Digital Converter. A chip containing the design has been sent away for fabrication. Because of the long processing time, no measurement data are presented. The main specifications for the voltage reference generator is to generate stable reference voltages with low noise and a good PSRR. Efforts has also been made to minimize the power consumption.</p>