With the increment of mobile, biomedical and space applications, digital systems with low-power consumption are required. As a main part in digital systems, low-power memories are especially desired. Reducing the power supply voltages to sub-threshold region is one of the effective approaches for ultra low-power applications. However, the reduced Static Noise Margin (SNM) of Static Random Access Memory (SRAM) imposes great challenges to the subthreshold SRAM design. The conventional 6-transistor SRAM cell does not function properly at sub-threshold supply voltage range because it has no enough noise margin for reliable operation. In order to achieve ultra low-power at sub-threshold operation, previous research work has demonstrated that the read and write decoupled scheme is a good solution to the reduced SNM problem. A Dual Interlocked Storage Cell (DICE) based SRAM cell was proposed to eliminate the drawback of conventional DICE cell during read operation. This cell can mitigate the singleevent effects, improve the stability and also maintain the low-power characteristic of subthreshold SRAM, In order to make the proposed SRAM cell work under different power supply voltages from 0.3 V to 0.6 V, an improved replica sense scheme was applied to produce a reference control signal, with which the optimal read time could be achieved. In this thesis, a 2K~8 bits SRAM test chip was designed, simulated and fabricated in 90nm CMOS technology provided by ST Microelectronics. Simulation results suggest that the operating frequency at VDD = 0.3 V is up to 4.7 MHz with power dissipation 6.0 ÊW, while it is 45.5 MHz at VDD = 0.6 V dissipating 140 ÊW. However, the area occupied by a single cell is larger than that by conventional SRAM due to additional transistors used. The main contribution of this thesis project is that we proposed a new design that could simultaneously solve the ultra low-power and radiation-tolerance problem in large capacity memory design.

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Thesis (M.S.)--Ohio University, March, 1993. / Title from PDF t.p.

This thesis deals with tests of forming operations, which are used to determine coefficient of friction. In the theoretical part of thesis, the individual tests are described in details, with the greatest emphasis on the upsetting test. In the experimental part of thesis was perform upsetting test on the cylindrical and ring samples. Coefficient of friction of the cylindrical samples was determined by a calculation method and ring samples were evaluated using diagram of calibration. The thesis includes comparison of the result received on lubricant and unlubricated samples and method for determined coefficient of friction. Graphite Delta 144 was used as a lubricant. This result show that the lubricant has a positive effect on forming process.

A method for measuring system-on-a-chip (SoC) cache upsets is presented and evaluated. In contrast to methods that predict cache contents through analysis or memory access patterns, this method uses system registers to read cache memories directly, thereby creating and checking golden copies to detect individual memory upsets during operation. The test method is driven by the device under test itself and does not require a user to set or know a priori the cache contents. A bare-metal implementation of this “direct golden method” on a Zynq UltraScale+ MPSoC logged upsets in the device’s data cache, data tag, and TLB RAM memories during a neutron radiation beam test. For each of these memories, this direct golden method yields cache upset bit cross sections, such as 7.115 × 10^−16 cm^2 for the data cache. Confidence intervals for these bit cross sections overlap such intervals for three other methods, supporting this method’s validity and candidacy for future use.

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L'environnement radiatif spatial provoque des anomalies dans les systèmes informatiques embarques. Il est donc primordial de définir des stratégies de qualification permettant le choix du circuit le moins vulnérable. Le phénomène dit d'Upset est l'un des effets du rayonnement le plus critique pour les circuits intégrés. Les différentes stratégies de test d'Upset sont passées en revue, dans le cas des circuits intégrés programmables. Un équipement expérimental de test a été développé et une methode de test a été appliquée a des circuits candidats a des applications spatiales. Les tests aux ions lourds ont été réalisés a l'aide de différents simulateurs d'ions lourds (source de californium, cyclotron, synchrotron), validant ainsi le matériel et l'approche développes et donnant des indications sur l'efficacité de ces simulations

La réduction des dimensions et paramètres électriques des transistors, fruit des progrès dans les technologies de fabrication de circuits intégrés, rend les composants présents et futurs de plus en plus sensibles aux perturbations appelées évènements singuliers S.E.E. (Single Event Effects). Ces événements sont la conséquence d'une impulsion de courant résultant de l'impact dans des zones sensibles du circuit, de particules énergétiques présentes dans l'environnement dans lequel ils fonctionnent. Parmi les différents types de SEE, peuvent être mentionnés les SEU (Single Event Upsets) qui consistent en l'inversion du contenu de cellules mémoires, les SEL (Single Event Latchups) qui donnent lieu à des courts-circuits masse-alimentation et peuvent donc conduire à la destruction du circuit par effet thermique. Cette thèse a pour but de décrire et valider les méthodologies nécessaires pour évaluer de manière précise la sensibilité face aux radiations de deux types de circuits numériques représentatifs, processeurs et mémoires, composants utilisés dans la plupart des systèmes embarqués.

<p>Nuclear particles hitting the silicon in a electronic device can cause a change in the data in a memory bit cell or in a flip-flop. The device is still working, but the data is corrupted and this is called a soft error. A soft error caused by a single nuclear particle is called a single event upset and is a growing problem. Research is ongoing at Saab aiming at how susceptible random access memories are to protons and neutrons.</p><p>This thesis describes the development of equipment for measuring cosmic-ray effects on DRAM in laboratories. The system is built on existing hardware with a FPGA as the core unit. A short history of soft errors is also given and what causes it. How a DRAM works and basic operation is explained and the difference between a SRAM. The result is a working system ready to be used.</p>

Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. High energy particles can ionize the semiconductor and lead to single event effects. For digital systems, the transients can upset the logic values in the storage cells which are called single event upsets, or in the combinational logic circuits which are called single event transients. While for analog systems, the transient will introduce noises and change the operating point. The influence becomes more notable in advanced technologies, where devices are more susceptive to the perturbations due to the compact layout. Recently radiation-hardened-by-design has become an effective approach compared to that of modifying semiconductor processes. Hence it is used in this thesis project. Firstly, three elaborately designed radiation-tolerant registers are implemented. Then, two built-in testing circuits are introduced. They are used to detect and count the single event upsets in the registers during high-energy particle tests. The third part is the pulse width measurement circuit, which is designed for measuring the single event transient pulse width in combinational logic circuits. According to the simulations, transient pulse width ranging from 90.6ps to 2.53ns can be effectively measured. Finally, two frequently used cross-coupled LC tank voltage-controlled oscillators are studied to compare their radiation tolerances. Simulation results show that the direct power connection and transistors working in the deep saturation mode have positive influence toward the radiation tolerance. All of the circuit designs, simulations and analyses are based on STMicroelectronics CMOS 90 nm 7M2T General Process.