With CdTe based photovoltaics developed by close spaced sublimation reaching efficiencies of over 16%, commercialization of this technology draws serious attention. Today large area industrial modules have not been able to produce the same performance of their laboratory counterparts. This work provides a means for understanding the various technical challenges in developing an effective deposition technology for large area processing. The submodule process investigated provides a model for continuous and sequential processing of subsequent films. The system has a unique design and constructed with the provision for a moving transport module for the substrate transport. The process was developed to deposit large area CdTe (3 x 3 sq. inch) and provides valuable insights for the development of a large area deposition system. Upon optimizing the system for reproducibility, proper deposition conditions were established. Films deposited under various conditions were studied to improve our understanding of the influence of processing conditions on device performance. The key advantage of this technique over others is its high deposition rate, simplicity of operation and high conversion efficiency. Typical deposition times were two minutes and could be reduced to as low as 45 sec with little variation in performance. The four major parameters that influence the films prepared by close spaced sublimation, namely substrate temperature, source temperature, ambient pressure, and spacing were optimized for best device performance. The influence of each parameter on deposition rate and cell efficiency was also studied. The best cells produced by this technology had an efficiency of 13% with Voc=830 mV, FF= 74% and Jsc=21.1 mA/cm2.

Title from PDF of title page. / Document formatted into pages; contains 78 pages. / Thesis (M.S.E.E.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT: With CdTe based photovoltaics developed by close spaced sublimation reaching efficiencies of over 16%, commercialization of this technology draws serious attention. Today large area industrial modules have not been able to produce the same performance of their laboratory counterparts. This work provides a means for understanding the various technical challenges in developing an effective deposition technology for large area processing. The submodule process investigated provides a model for continuous and sequential processing of subsequent films. The system has a unique design and constructed with the provision for a moving transport module for the substrate transport. The process was developed to deposit large area CdTe (3 x 3 sq. inch) and provides valuable insights for the development of a large area deposition system. Upon optimizing the system for reproducibility, proper deposition conditions were established. / ABSTRACT: Films deposited under various conditions were studied to improve our understanding of the influence of processing conditions on device performance. The key advantage of this technique over others is its high deposition rate, simplicity of operation and high conversion efficiency. Typical deposition times were two minutes and could be reduced to as low as 45 sec with little variation in performance. The four major parameters that influence the films prepared by close spaced sublimation, namely substrate temperature, source temperature, ambient pressure, and spacing were optimized for best device performance. The influence of each parameter on deposition rate and cell efficiency was also studied. The best cells produced by this technology had an efficiency of 13% with Voc=830 mV, FF= 74% and Jsc=21.1 mA/cm2. / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.

A process has been developed to make the dielectric layer for organic thin-film transistors (OTFTs) in a roll-to-roll vacuum web coater environment. This dielectric layer combined with an organic semiconductor layer and metal layer deposited in vacuum allows a solvent-free process to make organic/inorganic multilayer structures for thin-film electronic devices on a flexible substrate at, potentially, high speed. The polymeric gate dielectric layers were fabricated by flash evaporation of acrylic monomers onto a polymer film with pre-patterned metal gates followed by radiation curing by electron beam, ultra-violent light (UV) or plasma. With a non-polar dielectric surface, charge carrier mobility (μ) of 1 cm²-V^-1s^-1; on/off curren ratio of 10⁸, sub-threshold swing (SS) of 0.3 V/decade and saturated output curve were routinely achieved in dinaphtho-[2,3-b:2'3'-f]thieno[3,2-b]thiophene (DNTT) transistors with dielectric layer of tripropylene glycol diacrylate (TPGDA) of ~400 nm. Apart from the TPGDA, monomer formulas including 1,6-Hexanediol diacrylate (HDDA) as well as several commercial acrylic resins have been used to make the dielectric layer. The highest areal capacitance of 41nF-cm^-2 was achieved with a pin-hole free film of less than 100 nm made of an acrylate mixture resin. A non-polar dielectric surface treatment layer has been developed based on flash evaporation of lauryl acrylate and HDDA mixture. The transistors with the buffer layer showed constant performance and a mobility fivefold greater than those of untreated samples. The effect of humidity, oxygen, and light during switching cycles of both pentacene and DNTT transistors were studied. Water and oxygen/illumination had a distinct effect on both pentacene and DNTT transistors. Oxygen leads to acceptor-like charge traps under illumination, which shifted the turn-on voltage (V_to) to more positive values. In contrast, water in transistors gave rise to donor-like charge traps, which shifted the V_to and the threshold voltage (V_T) more negatively. The DNTT devices showed good stability in dry air without encapsulation, while pentacene transistors degraded with either repeating measurement or long term storage. A DNTT transistor with a PS-coated TPGDA dielectric layer showed stable drain current (I_d) of ~105A under bias stress of the gate voltage (em>V_g) of -20V and the drain voltage (em>V_d) of -20V for at least 144 hours. The V_to shift after the stress was less than 5 V and was recoverable when the device was kept in dry air for a few days. Possible reasons for the V_to shift have been discussed.