This thesis includes three topics. The first topic is a low-variation 1 MHz clock generator. The second one is a high sensitivity linear voltage-to-frequency converter. The last one is a high-PSR bias circuit for NTSC SYNC separation. All of the circuits can be applied to related consumer electronic products. The low-variation 1 MHz clock generator includes a bias circuit which automatically compensates the drifting caused by temperature variations. Furthermore, the circuit contains neither BJTs nor diodes to reduce the area cost. The frequency variation is measured to be less than 2.55\% in the range of 0¢J~90¢J. The high sensitivity linear voltage-to-frequency converter is mainly constructed by a window comparator[11]. We analyze and improve the performance of accuracy to achieve both high accuracy and high sensitivity. The accuracy error is less than 1% and sensitivity is 84 KHz/V in the voltage range of 0.1V~0.8V. The high-PSR bias circuit for NTSC SYNC Separation is implemented by a bandgap reference which is controlled by a feedback loop to reduce the interference of the environment. The measurement variation of the bandgap reference is less than 1\% when the variation of power supply is 10\%. The sensitivity of the bandgap reference to temperature is measured to be 0.0006V/¢J.

The first topic of this thesis is to propose a novel voltage-to-frequency converter (VFC) to provide high sensitivity. The VFC circuit is composed of one current mirror, one current multiplier, and voltage window comparators. The proposed VFC tracks the variations of the stored charge of a built-in capacitor. The voltage window comparator monitors the voltage of the capacitor to determine whether the output is pulled high or pulled down. The worth-case linear range of the output frequency of the proposed VFC is 0 to 55 MHz provided that the input voltage is 0 to 0.9 V. The error is less than 9% while the power dissipation is 0.218 mW. The second topic is to carry out a novel CMOS current-mode high- speed sense amplifier (SA). The proposed SA is composed by cascading a current-mode sense amplifier and a voltage-mode sense amplifier. The small input impedance of the current-mode amplifier alleviates the loading effect on the bitlines of SRAM cells such that the sensing speed is enhanced. The voltage-mode amplifier is responsible for boosting the logic levels to full swing. The worst access time of the proposed design is found to be less than 1.26 ns with a 1 pF load on outputs. The power dissipation is merely 0.835 mW at 793 MHz.