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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

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Showing 1 to 2 of 2 (0.101 seconds)

Spelling suggestions: "subject:"waferlevel patterning"" "subject:"waferebene patterning""

1

Self-aligned graphene on silicon substrates as ultimate metal replacement for nanodevices

Iacopi, Francesca, Mishra, N., Cunning, B.V., Kermany, A.R., Goding, D., Pradeepkumar, A., Dimitrijev, S., Boeckl, J.J., Brock, R., Dauskardt, R.H. 22 July 2016 (has links) (PDF)
We have pioneered a novel approach to the synthesis of high-quality and highly uniform few-layer graphene on silicon wafers, based on solid source growth from epitaxial 3C-SiC films [1,2]. The achievement of transfer-free bilayer graphene directly on silicon wafers, with high adhesion, at temperatures compatible with conventional semiconductor processing, and showing record- low sheet resistances, makes this approach an ideal route for metal replacement method for nanodevices with ultimate scalability fabricated at the wafer –level.
graphene
wafer-level patterning
silicon carbide on silicon
adhesion
ddc:620
Graphen
Strukturierung
Siliciumcarbid
Adhäsion
2

Self-aligned graphene on silicon substrates as ultimate metal replacement for nanodevices

Iacopi, Francesca, Mishra, N., Cunning, B.V., Kermany, A.R., Goding, D., Pradeepkumar, A., Dimitrijev, S., Boeckl, J.J., Brock, R., Dauskardt, R.H. 22 July 2016 (has links)
We have pioneered a novel approach to the synthesis of high-quality and highly uniform few-layer graphene on silicon wafers, based on solid source growth from epitaxial 3C-SiC films [1,2]. The achievement of transfer-free bilayer graphene directly on silicon wafers, with high adhesion, at temperatures compatible with conventional semiconductor processing, and showing record- low sheet resistances, makes this approach an ideal route for metal replacement method for nanodevices with ultimate scalability fabricated at the wafer –level.
info:eu-repo/classification/ddc/620
ddc:620

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