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This thesis examines chaotic mixing in wavy-type channels and two-layer shallow water flow. For wavy-type channels, the equations of motion for vortices and fluid particles are derived assuming two-dimensional irrotational, incompressible flow. Instantaneous positions of the vortices and particles are determined using Lagrangian tracking, and are conformally mapped to the physical domain. Unsteady vortex motion is analysed, and vortex-induced chaotic mixing in the channels studied. The dynamics of mixing associated with the evolution of the separation bubble, and the invariant manifolds are examined. Mixing efficiencies of the different channel configurations are compared statistically. Fractal enhancement of productivity is identified in the study of auto-catalytic reaction in the wavy channel. For the two-layer shallow water model, an entropy-correction free Roe type two-layer shallow water solver is developed for a hyperbolic system with non-conservative products and source terms. The scheme is well balanced and satisfies the C-property such that smooth steady solutions are second order accurate. Numerical treatment of the wet-dry front of both layers and the loss of hyperbolicity are incorporated. The solver is tested rigorously on a number of 1D and 2D benchmark test cases. For 2D implementation, a dynamically adaptive quadtree grid generation system is adopted, giving results which are in excellent agreement with those on regular grids at a much lower cost. It is also shown that algebraic balancing cannot be applied directly to a two-layer shallow water flow due to the lack of simultaneous referencing for the still water position for both layers. The adaptive two-layer shallow water solver is applied successfully to flow in an idealised tidal channel and to tidal-driven flow in Tampa Bay, Florida. Finally, chaotic advection and particle mixing is studied for wind-induced recirculation in two-layer shallow water basins, as well as Tampa Bay, Florida.

Wavy type Single Chamber Solid Oxide Fuel Cells (SC-SOFCs) have been shown to be conducive to improving the effective electrochemical reaction area contributing to higher performance, compared with planar type SC-SOFCs of the same diameter. This study presents a fabrication process for wavy type SC-SOFCs with a single fabrication step via co-sintering of a triple-layer structure. The monitoring and observation of the curvature evolution of bi- and triple-layer structures during co-sintering has resulted in an improved process with reduced manufacturing time and effort, as regards the co-sintering process for multi-layer structures. Investigation using in-situ monitoring helps different shrinkage behaviours of each porous layer to minimise mismatched stresses along with avoidance of severe warping and cracking. In the co-sintering of the multi-layer structures, the induced in-plane stresses contribute to curvature evolution in the structure, which can be utilised in the design of a curved multi-layer structure via the co-sintering process. For intermediate temperature SOFCs, the materials used are NiO/CGO for anode; CGO for electrolyte; and LSCF for cathode. These materials are tape-casted with 20μm thickness and assembled for bi- and triple-layer structures by hot pressing. Sintering mismatch stresses have been analysed in bi-layer structures, consisting of NiO/CGO-CGO and CGO-LSCF. The maximum sintering mismatch stress was calculated at interface of bi-layer structure in the top layer. In order to achieve the desired wavy type triple-layer structure, flexible green layers of each component were stacked up and laid on alumina rods to support the curvature during the process. In-situ observation, to monitor the shrinkage of each material and the curvature evolution of the structures, was performed using a long focus microscope (Infinity K-2). With these values, the main factors such as viscosity, shrinkage rate of each material, and curvature rate are investigated to determine the sintering mismatch stresses. This enables the prediction of curvature for triple-layer structure and the prediction is validated by in-situ monitoring of the triple-layer structure co-sintering process. Zero-deflection condition is confirmed to maintain initial shape during co-sintering and helps to minimise the development of undesired curvature in the triple-layer structure. Performance testing of the wavy cell was carried out in a methane-air mixture (CH4:O2 =1:1). In comparison with a planar SC-SOFC, it showed higher OCV which might be attributed to not only macro deformation, but also microstructural distribution affecting the effective gas diffusion paths and electrochemical active sites.

Information anytime and anywhere has ushered in a new technological age where massive amounts of ‘big data’ combined with self-aware and ubiquitous interactive computing systems is shaping our daily lives. As society gravitates towards a smart living environment and a sustainable future, the demand for faster and more computationally efficient electronics will continue to rise. Keeping up with this demand requires extensive innovation at the transistor level, which is at the core of all electronics. Up until recently, classical silicon transistor technology has traditionally been weary of disruptive innovation. But with the aggressive scaling trend, there has been two dramatic changes to the transistor landscape. The first was the re-introduction of metal/high-K gate stacks with strain engineering in the 45 nm technology node, which enabled further scaling on silicon to smaller nodes by alleviating the problem of gate leakage and improving the channel mobility. The second innovation was the use of non-planar 3D silicon fins as opposed to classical planar architectures for stronger electrostatic control leading to significantly lower off-state leakage and other short-channel effects. Both these innovations have prolonged the life of silicon based electronics by at least another 1-2 decades. The next generation 14 nm technology node will utilize silicon fin channels that have gate lengths of 14 nm and fin thicknesses of 7 nm. These dimensions are almost at the extreme end of current lithographic capabilities. Moreover, as fins become smaller, the parasitic capacitances and resistances increase significantly resulting in degraded performance. It is of popular consensus that the next evolutionary step in transistor technology is in the form of gate-all-around silicon nanowires (GAA NWFETs), which offer the tightest electrostatic configuration leading to the lowest possible leakage and short channel characteristics in over-the-barrier type devices. However, to keep scaling on silicon, the amount of current generated per device has to be increased while keeping short channel effects and off-state leakage at bay. The objective of this doctoral thesis is the investigation of an innovative vertical silicon based architecture called the silicon nanotube field effect transistor (Si NTFET). This topology incorporates a dual inner/outer core/shell gate stack strategy to control the volume inversion properties in a hollow silicon 1D quasi-nanotube under a tight electrostatic configuration. Together with vertically aligned source and drain, the Si NTFET is capable of very high on-state performance (drive current) in an area-efficient configuration as opposed to arrays of gate-all-around nanowires, while maintaining leakage characteristics similar to a single nanowire. Such a device architecture offsets the need of device arraying that is needed with fin and nanowire architectures. Extensive simulations are used to validate the potential benefits of Si NTFETs over GAA NWFETs on a variety of platforms such as conventional MOSFETs, tunnel FETs, junction-less FETs. This thesis demonstrates a novel CMOS compatible process flow to fabricate vertical nanotube transistors that offer a variety of advantages such as lithography-independent gate length definition, integration of epitaxially grown silicon nanotubes with spacer based gate dielectrics and abrupt in-situ doped source/drain junctions. Experimental measurement data will showcase the various materials and processing challenges in fabricating these devices. Finally, an extension of this work to topologically transformed wavy channel FinFETs is also demonstrated keeping in line with the theme of area efficient high-performance electronics.

This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Transistors. Through the use of inner/outer core-shell gates, heterostructure NT TFET leverages physically larger tunneling area thus achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. We discuss the physics of p-type (Silicon/Indium Arsenide) and n-type (Silicon/Germanium hetero-structure) based TFETs. Numerical TCAD simulations have shown that NT TFETs have 5x and 1.6 x higher normalized ION when compared to GAA NW TFET for p and n-type TFETs, respectively. This is due to the availability of larger tunneling junction cross sectional area, and lower Shockley-Reed-Hall recombination, while achieving sub 60 mV/dec performance for more than 5 orders of magnitude of drain current, thus enabling scaling down of Vdd to 0.5 V. This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving rise to up to 50% larger device width, without occupying extra chip area. The novel architecture shows 2x higher output drive current per unit chip area when compared to conventional planar architecture. The current increase is attributed to both the extra device width and 50% enhancement in field effect mobility due to electrostatic gating effects. Digital circuits are fabricated to demonstrate the potential of integrating WC TFT based circuits. WC inverters have shown 2× the peak-to-peak output voltage for the same input, and ~2× the operation frequency of the planar inverters for the same peak-to-peak output voltage. WC NAND circuits have shown 2× higher peak-to-peak output voltage, and 3× lower high-to-low propagation delay times when compared to their planar counterparts. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts. Finally, a WC based pass transistor logic multiplexer circuit is demonstrated, which has shown more than 5× faster high-to-low propagation delay compared to its planar counterpart at a similar peak-to-peak output voltage.

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Thermoelectric generators (TEGs) are currently being explored for their potential in harvesting energy from automobile exhaust. TEGs in form of an appropriate TEG- Heat exchanger module can utilize the temperature difference between the hot exhaust gases and the automobile coolant and convert it into electrical voltage. The amount of power is anticipated to be a few hundred watts depending on the temperature gradient and the material of the TEGs. The focus of this study is increasing the hot side heat transfer for improved performance of the thermoelectric generators using two different internal fins — louvered fins and herringbone wavy fins. The multi-louvered fins basically have 'multi flat plate' behavior and will enhance the heat transfer by deflecting the air from its original path and aligning it with the plane of the louvers. Herringbone fins are used to lengthen the path of airflow allowing for greater residence time and better mixing of the flow. They also provide for greater wetted surface area achieving higher heat transfer. The flow and heat transfer behavior inside the exhaust pipe test section with internal fins is modeled using commercial numerical software. The thermal and flow behavior through both these internal fins depends to a large extent on geometric parameters and fin arrangement. Optimization of the fin design is considered to determine the configuration that provides highest heat transfer while providing least pressure drop across the pipe length. The heat transfer and pressure drop characteristics are compared to the baseline flow without any fin enhancement. / Master of Science