<p>In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers.</p><p>The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.</p>
Identifer | oai:union.ndltd.org:UPSALLA/oai:DiVA.org:liu-8706 |
Date | January 2007 |
Creators | Öresjö, Per |
Publisher | Linköping University, Department of Electrical Engineering, Institutionen för systemteknik |
Source Sets | DiVA Archive at Upsalla University |
Language | English |
Detected Language | English |
Type | Student thesis, text |
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