Abstract A 10-bit 1MSample/sec successive approximation A/D converter is described in this thesis. First, by a comparator designed with high input impedance is used for the load of the modified wide-swing R-2R D/A converter. The modified wide-swing R-2R D/A converter possesses a high impedance load thus the op-amp is used in the D/A converter can be neglected. Therefore, the usable swing range and the convertible speed are improved and the power consumption is reduced. Secondary, the modified wide-swing R-2R D/A converter that contains modified switch-circuit and matched-component is used to obtain the good voltage division thereby improving the accuracy. Finally, the modified timing skew-insensitive double-sampling S/H circuit is used to sample a high precision signal to the comparator. This modified timing skew-insensitive double-sampling S/H circuit consists of high-gain high-swing op-amp, CMOS dummy switches, and timing skew-insensitive technique for upgrading the precision and swing range. By using these improved circuits the overall speed, accuracy and swing range are improved. The proposed successive approximation A/D converter is designed by TSMC 1P4M 0.35£gm CMOS process, and it operates at 3.3V power supply voltage with 0.8 to 2.9V reference voltage. The simulation results show that DNL is 0.5LSB, INL is 1LSB, and the power consumption is 8mW.

Analog-to-digital (A/D) conversion is a process that bridges the real analog world to digital signal processing. It takes a continuous-time, continuous amplitude signal as its input and outputs a discrete-time, discrete-amplitude signal. The resolution and sampling rate of an A/D converter vary depending on the application. Recently, there has been a growing demand for broadband (>1 MHz), high-resolution (>14bits) A/D converters. Applications that demand such converters include asymmetric digital subscriber line (ADSL) modems, cellular systems, high accuracy instrumentation, and medical imaging systems. This thesis suggests some design techniques for such high resolution and high sampling rate A/D converters. As the A/D converter performance keeps on increasing it becomes increasingly difficult for the input driver to settle to required accuracy within the sampling time. This is because of the use of larger sampling capacitor (increased resolution) and a decrease in sampling time (higher speed). So there is an increasing trend to have a driver integrated onchip along with A/D converter. The first contribution of this thesis is to present a new precharge scheme which enables integrating the input buffer with A/D converter in standard CMOS process. The buffer also uses a novel multi-path common mode feedback scheme to stabilize the common mode loop at high speeds. Another major problem in achieving very high Signal to Noise and Distortion Ratio (SNDR) is the capacitor mismatch in Digital to Analog Converters (DAC) inherent in the A/D converters. The mismatch between the capacitor causes harmonic distortion, which may not be acceptable. The analysis of Dynamic Element Matching (DEM) technique as applicable to broadband data-converters is presented and a novel second order notch-DEM is introduced. In this thesis we present a method to calibrate the DAC. We also show that a combination of digital error correction and dynamic element matching is optimal in terms of test time or calibration time. Even if we are using dynamic element matching techniques, it is still critical to get the best matching of unit elements possible in a given technology. The matching obtained may be limited either by random variations in the unit capacitor or by gradient effects. In this thesis we present layout techniques for capacitor arrays, and the matching results obtained in measurement from a test-chip are presented. Thus we present various design techniques for high speed and low noise A/D converters in this thesis. The techniques described are quite general and can be applied to most of the types of A/D converters.

With the development of economy, more and more cars appear in the roads. Many drivers ignore thedanger about driving after drinking so that drunk driving causes a large number of traffic accidents allaround the world. By now, alcohol has killed a lot of people in the world. To reduce accidents causedby drunk driving, make certain the alcohol content in driver's body would help a lot, and it is related toalcohol concentration measuring and relevant instrument.In this thesis work, the design of a simple alcohol meter was present. The designed system iscomposed of a gas sensor (TGS-822) working circuit, microcontroller PIC16F690 and LCD display.The system collects the electronic signals caused by resistance changes in gas sensor (TGS-822) froma built-in Analog-to-Digital Converter (A/D) in microcontroller PIC16F690, programs withPIC16F690, and displays alcohol concentration in LCD display finally. The measuring concentrationrange of the designed alcohol meter is from 50PPM to 5000PPM. This paper describes the datacollection, processing and display of the designed alcohol meter in detail. And lastly, the authordiscussed about the advantages and disadvantages of the designed alcohol meter, it could beconsidered as a guideline for further work.

"This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The ‘split ADC’ is a new concept that allows the use of a deterministic, digital, self calibrating algorithm. In this approach, an ADC is split into two paths, producing two output codes from the same input sample. The difference of these two codes is used as the calibration signal for an LMS error estimation algorithm that drives the difference error to zero. The ADC is calibrated when the codes are equal and the output is taken as the average of the two codes. The ‘split’ ADC concept and interleaved architecture are combined in this IC design to form the core of a high speed, high resolution, and self-calibrating ADC system. The dual outputs are used to drive a digital calibration engine to correct for the channel mismatch errors. This system has the speed benefits of interleaving while maintaining high resolution. The hardware for the algorithm as well as the ADC can be implemented in a standard 0.25um CMOS process, resulting in a relatively inexpensive solution. This work is supported by grants from Analog Devices Incorporated (ADI) and the National Science Foundation (NSF). "

<p>In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers.</p><p>The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.</p>

In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers. The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.

This dissertation deals with a development of MCU position steering application of two servomotors and with data process evaluation from a connected sensor for distance measuring as well. The connected sensor is adjustable as for azimuth and elevation. Data from the sensor will be useful both for instant evaluation according to preset criteria and for additional possible processing at PC. The development is to be carry out at MCU ATmega128. HMI is represented with keyboard, LCD and joystick. The result of the dissertation is to be adjusted for practical demo. This research has been supported by the Czech Ministry of Education in the frame of MSM 0021630529 Research Intention Inteligent Systems in Automation.

The goal of this thesis is create measuring station of resolver with using Analog Devices AD2S1210. The measuring station is based on the Atmel ATmega16 microprocesor and programmed in the C language. The measuring plant of resolvers to detection fault per one revolution is developed with industrial cooperation. The measuring station is made for a mobile use with onboard Pb accu. Measuring station will be used as a service device or in the manufacturing for setting the right angle of resolver on the engine. For the faults debugging of resolvers cables and other faults with the signal chain between the resolver and AD2S1210 is possible to show the SIN and COS signals on the external scope.

This thesis describes the design of portable multi-purpose measuring device with Microcontrollers from Microchip running on battery power, for displaying the measured signal uses a graphical LCD with a resolution of 240x128. The device is equipped with an oscilloscope and multimeter with auto range.

The ever-increasing resolution of CMOS imagers has steadily driven the requirements of readout circuitry. As the number of sensors on a chip increases, the bandwidth of the readout circuit must be increased correspondingly to maintain a constant frame rate. Column parallel A/D converters are commonly used to divide the conversions among many converters. However, implementing high-speed, high-resolution A/D converters at the column level is challenging because the entire circuit needs to be as narrow as the sensor. This thesis presents the design of a 10-bit, one million conversions per second column-parallel A/D converter. A factor of four increase in speed over conventional converters was achieved by combining techniques of successive approximation and two-step subranging in a distributed column-parallel architecture. The speed of the converter makes it suitable to be integrated with a 1-megapixel sensor array providing a frame rate at 1000fps with 11µm pixels in a 0.35µm CMOS technology.