CMOS imagers are replacing CCD imagers in many applications and will continue to make new applications possible. CMOS imaging offers lower cost implementations on standard CMOS processes which allow for mixed signal processing on-chip. A system-on-a-chip approach offers the ability to perform complex algorithms faster, in less space, and with lower power and noise. Our transform imager is an implementation of a mixed focal plane and peripheral computation imager which allows high fill factor with high computational rates at low power. However, in order to use the technology effectively a need to verify and further understand the behavior and of the pixel elements in this transform imager was needed. This thesis presents a study of the pixel elements and mismatches and errors in the pixel array of this imager. From there, a discussion about removing offsets and an implementation of a circuit to remove the largest offsets is shown. To further enhance performance, initial work to develop light adaptive readout circuits is presented. Finally, an overview is given of a newly designed one-megapixel transform imager with many design improvements.

This thesis presents two hybrid luminescence-based biochemical photosensory microsystems: a CMOS/microfluidic chemiluminescence contact imager, and a CMOS/thin-film fluorescence contact imager. A compact, low-power analog-to-digital converter (ADC) architecture for use in such sensory microsystems is also proposed. Both microsystems are prototyped in a standard 0.35um CMOS technology. The CMOS/microfluidic microsystem integrates a 64x128-pixel CMOS imager and a soft polymer microfluidic network. Circuit techniques are employed to reduce the dark current and circuit noise for low-level light sensitivity. Experimental validation is performed by detecting luminol chemiluminescence and electrochemiluminescence. The CMOS/thin-film microsystem integrates an existing 128x128-pixel CMOS imager and a prefabricated, high-performance optical filter. Experimental validation is performed by detecting human DNA labeled with Cyanine-3 fluorescent dye. The proposed ADC architecture employs a novel digital-to-analog converter with a flexible trade-off between the integration area and the conversion speed. The area savings and good linearity of the DAC are verified by simulations.

This thesis presents two hybrid luminescence-based biochemical photosensory microsystems: a CMOS/microfluidic chemiluminescence contact imager, and a CMOS/thin-film fluorescence contact imager. A compact, low-power analog-to-digital converter (ADC) architecture for use in such sensory microsystems is also proposed. Both microsystems are prototyped in a standard 0.35um CMOS technology. The CMOS/microfluidic microsystem integrates a 64x128-pixel CMOS imager and a soft polymer microfluidic network. Circuit techniques are employed to reduce the dark current and circuit noise for low-level light sensitivity. Experimental validation is performed by detecting luminol chemiluminescence and electrochemiluminescence. The CMOS/thin-film microsystem integrates an existing 128x128-pixel CMOS imager and a prefabricated, high-performance optical filter. Experimental validation is performed by detecting human DNA labeled with Cyanine-3 fluorescent dye. The proposed ADC architecture employs a novel digital-to-analog converter with a flexible trade-off between the integration area and the conversion speed. The area savings and good linearity of the DAC are verified by simulations.

Camera-on-a-chip systems have tried to include carefully chosen signal processing units for better functionality, performance and also to broaden the applications they can be used for. Image processing sensors have been possible due advances in CMOS active pixel sensors (APS) and neuromorphic focal plane imagers. Some of the advantages of these systems are compact size, high speed and parallelism, low power dissipation, and dense system integration. One can envision using these chips for portable and inexpensive video cameras on hand-held devices like personal digital assistants (PDA) or cell-phones In neuromorphic modeling of the retina it would be very nice to have processing capabilities at the focal plane while retaining the density of typical APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our MAtrix Transform Imager Architecture (MATIA) that uses analog floating--gate devices to make it possible to have computational imagers with high pixel densities. The core imager performs computations at the pixel plane, but still has a fill-factor of 46 percent - comparable to the high fill-factors of APS imagers. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image. The resulting data-flow architecture can directly perform all kinds of block matrix image transforms. Since the imager operates in the subthreshold region and thus has low power consumption, this architecture can be used as a low-power front end for any system that utilizes these computations. Various compression algorithms (e.g. JPEG), that use block matrix transforms, can be implemented using this architecture. Since MATIA can be used for gradient computations, cheap image tracking devices can be implemented using this architecture. Other applications of this architecture can range from stand-alone universal transform imager systems to systems that can compute stereoscopic depth.

This research focuses on the implementation of the efficient image compression system among the many potential applications of a transform imager system. The study includes implementing the image compression system using a transform imager, developing a novel image compression algorithm for the system, and improving the performance of the image compression system through efficient encoding and decoding algorithms for vector quantization. A transform imaging system is implemented using a transform imager, and the baseline JPEG compression algorithm is implemented and tested to verify the functionality and performance of the transform imager system. The computational reduction in digital processing is investigated from two perspectives, algorithmic and implementation. Algorithmically, a novel wavelet-based embedded image compression algorithm using dynamic index reordering vector quantization (DIRVQ) is proposed for the system. DIRVQ makes it possible for the proposed algorithm to achieve superior performance over the embedded zero-tree wavelet (EZW) algorithm and the successive approximation vector quantization (SAVQ) algorithm. However, because DIRVQ requires intensive computational complexity, additional focus is placed on the efficient implementation of DIRVQ, and highly efficient implementation is achieved without a compromise in performance.

abstract: Global industrialization and urbanization have led to increased levels of air pollution. The costs to society have come in the form of environmental damage, healthcare expenses, lost productivity, and premature mortality. Measuring pollutants is an important task for identifying its sources, warning individuals about dangerous exposure levels, and providing epidemiologists with data to link pollutants with diseases. Current methods for monitoring air pollution are inadequate though. They rely on expensive, complex instrumentation at limited fixed monitoring sites that do not capture the true spatial and temporal variation. Furthermore, the fixed outdoor monitoring sites cannot warn individuals about indoor air quality or exposure to chemicals at worksites. Recent advances in manufacturing and computing technology have allowed new classes of low-cost miniature gas sensor to emerge as possible alternatives. For these to be successful however, there must be innovations in the sensors themselves that improve reliability, operation, and their stability and selectivity in real environments. Three novel gas sensor solutions are presented. The first is the development of a wearable personal exposure monitor using all commercially available components, including two metal oxide semiconductor gas sensors. The device monitors known asthma triggers: ozone, total volatile organic compounds, temperature, humidity, and activity level. Primary focus is placed on the ozone sensor, which requires special circuits, heating algorithm, and calibration to remove temperature and humidity interferences. Eight devices are tested in multiple field tests. The second is the creation of a new compact optoelectronic gas sensing platform using colorimetric microdroplets printed on the surface of a complementary-metal-oxide-semiconductor (CMOS) imager. The nonvolatile liquid microdroplets provide a homogeneous, uniform environment that is ideal for colorimetric reactions and lensless optical measurements. To demonstrate one type of possible indicating system gaseous ammonia is detected by complexation with Cu(II). The third project continues work on the CMOS imager optoelectronic platform and develops a more robust sensing system utilizing hydrophobic aerogel particles. Ammonia is detected colorimetrically by its reaction with a molecular dye, with additives and surface treatments enhancing uniformity of the printed films. Future work presented at the end describes a new biological particle sensing system using the CMOS imager. / Dissertation/Thesis / Doctoral Dissertation Materials Science and Engineering 2020

The ever-increasing resolution of CMOS imagers has steadily driven the requirements of readout circuitry. As the number of sensors on a chip increases, the bandwidth of the readout circuit must be increased correspondingly to maintain a constant frame rate. Column parallel A/D converters are commonly used to divide the conversions among many converters. However, implementing high-speed, high-resolution A/D converters at the column level is challenging because the entire circuit needs to be as narrow as the sensor. This thesis presents the design of a 10-bit, one million conversions per second column-parallel A/D converter. A factor of four increase in speed over conventional converters was achieved by combining techniques of successive approximation and two-step subranging in a distributed column-parallel architecture. The speed of the converter makes it suitable to be integrated with a 1-megapixel sensor array providing a frame rate at 1000fps with 11µm pixels in a 0.35µm CMOS technology.

No description available.

Le test de production des imageurs CMOS est une étape clé du flot de fabrication afin de garantir des produits répondant aux critères de qualité et exempts de défauts de fabrication. Ces tests sont classifiés en test électrique et test optique. Le test électrique est basé sur du test structurel qui vérifie la partie numérique et certain blocks analogiques. La plus grande partie des circuits analogiques et la matrice des capteurs sont testés par le test optique. Ce test est basé sur des captures d'images et sur une recherche des défauts au moyen d'algorithmes de calcul spécifiques appliqué sur les images. Proche du fonctionnement applicatif, ils sont qualifies de test fonctionnels. La couverture des défauts obtenue par les tests de type fonctionnel est généralement inférieure à celle obtenue par un test structurel. L'objectif de cette thèse est d'étudier et développer des solutions de test alternatives aux tests fonctionnels afin d'obtenir des meilleurs taux de couverture de défauts, améliorant ainsi la fiabilité, tout en réduisant le temps de test et son coût. Parmi les défauts optiques qui ont causé des retours client par le passés, le défaut qui présent Horizontal Fixed Pattern Noise (HFPN) donnent lieu à un taux de couverture insuffisant. Ces recherches ont été orientées vers l'amélioration du taux de couverture de défauts dite de HFPN dans le test de production des imageurs CMOS.Le HFPN est défini comme une sorte d'image défaillante qui présente sous la forme des bandes résiduelles horizontales. Il est principalement causé par les défauts dans les lignes d'interconnexion qui alimentent et pilotent les pixels. La détection d'un défaut HFPN dans les tests optiques actuels est par comparer les valeurs moyennes de chaque ligne de pixels avec les lignes adjacentes. Si la différence d'une ligne par rapport aux lignes adjacentes est supérieur à la limites spécifié, la ligne est constaté comme défectueuse. Cette limite est donc difficile d'être ajusté face à un compromis entre le taux de couverture de ce défaut et le rendement.Dans cette thèse, nous avons proposé d'abord une amélioration de l'algorithme de détection pour améliorer le test optique actuelle. L'amélioration de test optique est validée par des résultats de test en production en appliquant le nouvel algorithme. Par la suite, une technique d'auto test (BIST) pour la détection des défauts dans les lignes d'interconnexion de matrice des pixels est étudiée et évalué. Enfin, une puce imageur avec le technique d'auto test embarqué est conçu et fabriqué pour la validation expérimentale. / Current production testing of CMOS imager sensors is mainly based on capturing images and detecting failures by image processing with special algorithms. The fault coverage of this costly optical test is not sufficient given the quality requirements. Studies on devices produced at large volume have shown that Horizontal Fixed Pattern Noise (HFPN) is one of the common image failures encountered on products that present fault coverage problems, and this is the main cause of customer returns for many products. A detailed analysis of failed devices has demonstrated that HFPN failures arise from changes of electronic circuit topology in pixel addressing decoders or the metal lines required for pixel powering and control. These changes are usually due to the presence of spot defects, causing some pixels in a row to operate incorrectly, leading to an HFPN failure. Moreover, defects resulting in partially degraded metal lines may not induce image failure in limited industrial test conditions, passing the optical tests. Later, these defects may produce an image failure in the field, either because the capture conditions would be more stringent, or because the defects would evolve into catastrophic faults due to electromigration. In this paper, we have first enhanced the HFPN detection algorithm in order to improve the fault coverage of the optical test. Next, a built-in self-test structure is presented for the on-chip detection of catastrophic and non-catastrophic defects in the pixel power and control lines.

<p>The compressive sensing (CS) paradigm provides an efficient image acquisition technique through simultaneous sensing and compression. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures are required to design cameras suitable for CS imaging.</p> <p>While this work is focused on the hardware implementation of CS encoding for CMOS sensors, the image reconstruction problem of CS is also studied. The energy compaction properties of the image in different domains are exploited to modify conventional reconstruction problems. Experimental results show that the modified methods outperform the 1-norm and TV (total variation) reconstruction algorithms by up to 2.5dB in PSNR.</p> <p>Also, we have designed, fabricated and measured the performance of two real-time and area-efficient implementations of the CS encoding for CMOS imagers. In the first implementation, the idea of active pixel sensor (APS) with an integrator and in-pixel current switches are used to develop a compact, current-mode implementation of CS encoding in analog domain. In another implementation, the conventional three-transistor APS structure and switched capacitor (SC) circuits are exploited to develop the analog, voltage-mode implementation of the CS encoding. With the analog and block-based implementation, the sensing and encoding are performed in the same time interval, thus making a real-time encoding process. The proposed structures are designed and fabricated in 130nm technology. The experimental results confirm the scalability, the functionality of the block read-out, and the validity of the design in making monotonic and appropriate CS measurements.</p> <p>This work also discusses the CS-CMOS sensors for high frame rate CS video coding. The method of multiple-camera with coded exposure video coding is discussed and a new pixel and array structure for hardware implementation of the method is presented.</p> / Doctor of Philosophy (PhD)