In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long time operation. As a fundamental building block of ADC, comparator should support a tightened power budget. Therefore, developing low-power design techniques for comparator is becoming more and more important.
As an alternative to the conventional voltage-mode comparator, this thesis proposed an energy efficient time-domain comparator, which uses digital circuits to process analog signals by representing them as timing information. The proposed time-domain comparator has three main features: comparing on both clock edges (rising/falling), asynchronous comparison and 2-bit/step comparison. With these features, power consumption of the comparator can be effectively reduced.
For verification, the proposed time-domain comparator is fabricated in IBM 0.18um CMOS technology in comparison with other two conventional time-domain comparators working at 100kS/s sampling rate and 8-bit resolution. The achieved power consumption of the proposed time-domain comparator is 50nW, which is much lower than 84nW and 285nW of the other two time-domain comparators.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/149314 |
| Date | 02 October 2013 |
| Creators | Gao, Yang |
| Contributors | Sanchez-Sinencio, Edgar, Butenko, Sergiy, Entesari, Kamran, Lu, Mi |
| Source Sets | Texas A and M University |
| Language | English |
| Detected Language | English |
| Type | Thesis, text |
| Format | application/pdf |
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