Approved for public release; distribution is unlimited / The contribution of this thesis is the development of a CAD (computer aided
design) tool for current mode multiple-valued logic (MVL) CMOS circuits. It is
only the second known MVL CAD tool and the first CAD tool for MVL CMOS.
The tool accepts a specification of the function to be realized by the user,
produces a minimal or near-minimal realization (if such a realization is possible),
and produces a layout of a programmable logic array (PLA) integrated circuit that
realizes the given function. The layout is in MAGIC format, suitable for submission
to a chip manufacturer. The CAD tool also allows the user to simulate the realized
function so that he/she can verify correctness of design.
The CAD tool is designed also to be an analysis tool for heuristic minimization
algorithms. As part of this thesis, a random function generator and statistics gathering
package were developed. In the present tool, two heuristics are provided and
the user can choose one or both. In the latter case, the better realization is output
to the user. The CAD tool is designed to be flexible, so that future improvements
can be made in the heuristic algorithms, as well as the layout generator. Thus,
the tool can be used to accommodate new technologies, for example, a voltage mode
CMOS PLA rather than the current mode CMOS currently implemented. / http://archive.org/details/cadtoolforcurren00leeh / Lieutenant, Republic of Korea Navy
| Identifer | oai:union.ndltd.org:nps.edu/oai:calhoun.nps.edu:10945/22935 |
| Date | 12 1900 |
| Creators | Lee, Hoon S. |
| Contributors | Butler, Jon T., Yurchak, J.M., Yang, C., Naval Postgraduate School (U.S.), Electrical Engineering |
| Publisher | Monterey, California. Naval Postgraduate School |
| Source Sets | Naval Postgraduate School |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Format | 114 p., application/pdf |
| Rights | Copyright is reserved by the copyright owner |
Page generated in 0.0021 seconds