現有不同種類的二進位邏輯(布林)轉換技術，用以改善二進位邏輯電路之各個範疇，包括面積、速度、耗電量及軟性錯誤率等等。有些邏輯轉換技術是基於代數運算，也有一些是基於邏輯理論。重新佈線是邏輯轉換技術的一種，特點是強而穩定且靈活。這種邏輯轉換技術的概念在於「以線換線」，即通過加入一些新電線(代替線），去移除電路內某些固有電線(目標線）。由於今天設計及製造電路之程序，已採用納米技術，電線之大小長短及布局均極影響電路的性能。因此，重新佈線技術很適用於現代的集成電路製作流程。本論文目的為研究傳統及新穎以誤差抵消為基礎的重新佈線技術之理論和應用，並試圖以其改善集成電路的耗電量與容錯能力。首先，我們研究採用重新佈線技術，去改善經過時鐘聞控技術處理的電路，減少其面積及耗電量。其次，我們結合以誤差抵消為基礎的重新佈線技術和傳統時鐘閘控技術，發展出新類型的時鐘閘控技術。最後，我們嘗試通過加添冗餘的電線來達到更佳的容錯能力。 / Various logic transformation techniques have been developed to optimize different aspects of Boolean circuit designs, such as area, speed, power and soft error rate. They range from algebraic operations to Boolean operations. Among the Boolean optimization techniques, rewiring is known to be as robust and flexible as others. Its idea is to replace a set of existing wires (target wires) in a circuit with another set of additional wires (alternative wires) which do not exist in the circuit originally. Hence, it is suitable for the design and manufacturing processes in today's nano-metre era in which wiring has become a dominating factor. In this thesis, a more general rewiring scheme based on the concepts of error cancellation as well as the traditional rewiring schemes were studied. Applications of rewiring and error cancellation concepts on power reduction and fault tolerance were experimented. Firstly, rewiring was adopted as a tool to minimize the area and power of clock gated circuits. Secondly, error-cancellation-based rewiring and traditional clock gating were integrated as a new kind of clock gating scheme. Lastly, a fault tolerance scheme based on redundant wire addition was developed. / Detailed summary in vernacular field only. / Lam, Tak Kei. / Thesis (Ph.D.) Chinese University of Hong Kong, 2014. / Includes bibliographical references (leaves 118-130). / Abstracts also in Chinese. / Lam, Tak Kei.

Thesis (Ph.D.) Dept. of Electrical and Electronic Engineering, University of Adelaide, 1979. / Typescript (photocopy).

No description available.

Thesis (Ph.D.)--University of Delaware, 2009. / Principal faculty advisor: Guang R. Gao, Dept. of Electrical & Computer Engineering. Includes bibliographical references.

Thesis (Ph. D.)--University of Washington, 2001. / Vita. Includes bibliographical references (leaves 91-97).

Typescript (photocopy) / vii, 190 leaves ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Thesis (Ph.D.) Dept. of Electrical and Electronic Engineering, University of Adelaide, 1979

Thesis (M.S.)--University of California, Berkeley, 1962. / "UC-32 Mathematics and Computers" -t.p. "TID-4500 (17th Ed.)" -t.p. Includes bibliographical references (p. 50-51).

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Paul Hasler; Committee Member: David V Anderson; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 90-92).

The subject of this dissertation is the theory of Boolean and multiple-valued functions. The main areas considered are: functional completeness, canonical forms, minimization of functions, discrete differences and functional decomposability. The results obtained are used as a foundation for the development of several new algorithms for logic synthesis of combinational logic circuits. These include an efficient algorithm for three-level AND-OR-XOR minimization for Boolean functions, an algorithm for generating the composition trees for Boolean and multiple-valued functions in a certain class, and an algorithm for computing a new canonical form of multiple-valued functions. Several other problems, related to logic synthesis, such as test generation for combinational logic circuits and synthesis of easily testable circuits are also addressed. Possible directions for future research are discussed. / Graduate