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Very Large Scale Integration (VLSI) deals with systems complexity rather than transistor size or circuit performance. VLSI design methodology is supported by Computer Aided Design (CAD) and Design Automation (DA) tools, which help VLSI designers to implement more complex and guaranteed designs. The increasing growth in VLSI complexity dictates a hierarchical design approach and the need for hardware DA tools. This paper discusses the generalized Design Procedure for CAD circuit design; the commercial CADs offered by CALMA and the Caesar System, supported by the Berkeley design tools. A complete design of a Content Addressable Memory (CAM) cell, using the Caesar system, supported by Berkeley CAD tools, is illustrated.

The performance of the Svoboda-Nadler-Vora algorithm for exact multiple-output boolean function minimization is studied and compared with a heuristic minimization method. For this purpose, the algorithm has been implemented in optimized ANSI C code. This implementation introduces a new set of procedures to reduce the cost of prime implicant generation. The concept of weight as the number of 1 and don't care neighbors of a state is used to take advantage of the special cases when a state has only one neighbor or no neighbors at all. The cost of prime implicant generation is further reduced by using the fact that the input dependency of any given state is limited by which of its neighbors exist within an output that are 1 's or don't cares. A detailed example illustrates how the heuristic method can fail to find the absolute minimum of a boolean function. / M.S.

The fundamental components for processing all-optically represented data, namely optical switches and logic gates are investigated. Improved techniques for fabricating nonlinear Fabry-Perot etalons containing GaAs have brought a proliferation of GaAs optical bistable devices. These devices show significant improvements in speed, power requirements, operating temperature and thermal stability. Experiments verify predictions that one can operate a single nonlinear etalon as optical logic gates or two such etalons as a flip-flop. Optimization of the logic gates is then discussed from a systems approach.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1981. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Bibliography: leaf 128. / by Andrew Lewis Ressler. / M.S.

Sze, Chin Ngai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 80-84) and index. / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Curriculum Vitae --- p.iv / List of Figures --- p.ix / List of Tables --- p.xii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Aims --- p.1 / Chapter 1.2 --- Contribution --- p.8 / Chapter 1.3 --- Organization of Dissertation --- p.10 / Chapter 2 --- Definitions and Notations --- p.11 / Chapter 3 --- Literature Review --- p.15 / Chapter 3.1 --- Logic Reconstruction --- p.15 / Chapter 3.1.1 --- SIS: A System for Sequential and Combinational Logic Synthesis --- p.16 / Chapter 3.2 --- ATPG-based Alternative Wiring --- p.17 / Chapter 3.2.1 --- Redundancy Addition and Removal for Logic Optimization --- p.18 / Chapter 3.2.2 --- Perturb and Simplify Logic Optimization --- p.18 / Chapter 3.2.3 --- REWIRE --- p.21 / Chapter 3.2.4 --- Implication-tree Based Alternative Wiring Logic Trans- formation --- p.22 / Chapter 3.3 --- Graph-based Alternative Wiring --- p.24 / Chapter 4 --- Implication Based Alternative Wiring Logic Transformation --- p.25 / Chapter 4.1 --- Source Node Implication --- p.25 / Chapter 4.1.1 --- Introduction --- p.25 / Chapter 4.1.2 --- Implication Relationship and Implication-tree --- p.25 / Chapter 4.1.3 --- Selection of Alternative Wire Based on Implication-tree --- p.29 / Chapter 4.1.4 --- Implication-tree Based Logic Transformation --- p.32 / Chapter 4.2 --- Destination Node Implication --- p.35 / Chapter 4.2.1 --- Introduction --- p.35 / Chapter 4.2.2 --- Destination Node Relationship --- p.35 / Chapter 4.2.3 --- Destination Node Implication-tree --- p.39 / Chapter 4.2.4 --- Selection of Alternative Wire --- p.41 / Chapter 4.3 --- The Algorithm --- p.43 / Chapter 4.3.1 --- IB AW Implementation --- p.43 / Chapter 4.3.2 --- Experimental Results --- p.43 / Chapter 4.4 --- Conclusion --- p.45 / Chapter 5 --- Graph Based Alternative Wiring Logic Transformation --- p.47 / Chapter 5.1 --- Introduction --- p.47 / Chapter 5.2 --- Notations and Definitions --- p.48 / Chapter 5.3 --- Alternative Wire Patterns --- p.50 / Chapter 5.4 --- Construction of Minimal Patterns --- p.54 / Chapter 5.4.1 --- Minimality of Patterns --- p.54 / Chapter 5.4.2 --- Minimal Pattern Formation --- p.56 / Chapter 5.4.3 --- Pattern Extraction --- p.61 / Chapter 5.5 --- Experimental Results --- p.63 / Chapter 5.6 --- Conclusion --- p.63 / Chapter 6 --- Logic Optimization by GBAW --- p.66 / Chapter 6.1 --- Introduction --- p.66 / Chapter 6.2 --- Logic Simplification --- p.67 / Chapter 6.2.1 --- Single-Addition-Multiple-Removal by Pattern Feature . . --- p.67 / Chapter 6.2.2 --- Single-Addition-Multiple-Removal by Combination of Pat- terns --- p.68 / Chapter 6.2.3 --- Single-Addition-Single-Removal --- p.70 / Chapter 6.3 --- Incremental Perturbation Heuristic --- p.71 / Chapter 6.4 --- GBAW Optimization Algorithm --- p.73 / Chapter 6.5 --- Experimental Results --- p.73 / Chapter 6.6 --- Conclusion --- p.76 / Chapter 7 --- Conclusion --- p.78 / Bibliography --- p.80 / Chapter A --- VLSI Design Cycle --- p.85 / Chapter B --- Alternative Wire Patterns in [WLFOO] --- p.87 / Chapter B.1 --- 0-local Pattern --- p.87 / Chapter B.2 --- 1-local Pattern --- p.88 / Chapter B.3 --- 2-local Pattern --- p.89 / Chapter B.4 --- Fanout-reconvergent Pattern --- p.90 / Chapter C --- New Alternative Wire Patterns --- p.91 / Chapter C.1 --- Pattern Cluster C1 --- p.91 / Chapter C.1.1 --- NAND-NAND-AND/NAND;AND/NAND --- p.91 / Chapter C.1.2 --- NOR-NOR-OR/NOR;AND/NAND --- p.92 / Chapter C.1.3 --- AND-NOR-OR/NOR;OR/NOR --- p.95 / Chapter C.1.4 --- OR-NAND-AND/NAND;AND/NAND --- p.95 / Chapter C.2 --- Pattern Cluster C2 --- p.98 / Chapter C.3 --- Pattern Cluster C3 --- p.99 / Chapter C.4 --- Pattern Cluster C4 --- p.104 / Chapter C.5 --- Pattern Cluster C5 --- p.105 / Glossary --- p.106 / Index --- p.108

The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems. This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits. The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good. The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent. One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.

Cube Calculus is an algebraic model popular used to process and minimize Boolean functions. Cube Calculus operations are widely used in logic optimization, logic synthesis, computer image processing and recognition, machine learning, and other newly developing applications which require massive logic operations. Cube calculus operations can be implemented on conventional general-purpose computers by using the appropriate "model" and software which manipulates this model. The price that we pay for this software based approach is severe speed degradation which has made the implementation of several high-level formal systems impractical. A cube calculus machine which has a special data path designed to execute multiplevalued input, and multiple-valued output cube calculus operations is presented in this thesis. This cube calculus machine can execute cube calculus operations 10-25 times faster than the software approach. For the purpose of ensuring the manufacturing testability of the cube calculus machine, emphasize has been put on the testability design of the cube calculus machine. Testability design and testability analysis of the iterative logic unit of the cube calculus machine was accomplished. Testability design and testability analysis methods of the cube calculus machine are weli discussed in this thesis. Full-scan testability design method was used in the testability design and analysis. Using the single stuck-at fault model, a 98.30% test coverage of the cube calculus machine was achieved. A Povel testability design and testability analysis approach is also presented in this thesis.

The primary metrics associated with a logic gate's performance are speed, power, and area. We define a gate as a specific CMOS transistor level implementation of a particu- lar boolean function in a specific fabrication technology at a constant rail voltage, constant length, and where the ratio of any two transistor widths are constant. Asking how fast a gate switches then is highly situational; it changes with load capacitance, choice of inputs, input slew rate, and the size of the gate. Predicting how much energy the gate consumes depends on the time frame, how many times the gate has switched in this time frame, input selection, input slew rate, load capacitance, and gate width. Logical Effort (LE) predicts gate delay with a simple linear equation: d = t(gh+p). Where g and p are gate and input dependent parameters independent of load size and gate size, and h is the ratio of output ca- pacitance to input capacitance (directly related to gate width), and t is a process dependent conversion factor. The product, gh, then is the delay associated with driving a subsequent gate, and p is the delay of the gate driving itself. The prediction ignores input slew rate and the linear dependence fails for very large values of h, but for input slew rates on the same order as the output slew rate, and for reasonable fan-outs, LE provides remarkably accurate predictions of gate switching time. The methodology goes on to solve for the widths nec- essary for each gate in an arbitrary logic path to minimize delay. Designs can quickly be compared, analyzed and optimized. By breaking down delay into components, one is able to intuitively choose better logic implementations, if parasitic delay is dominating, often a better implementation is one with smaller fan-in gates and less logic depth, if effort delay is dominating then then higher logic depth can lead to faster results. What the method does not do is predict the power consumption ramifications of all of these choices. What about minimizing power on non-critical paths, for instance? To our knowledge, no methodology exists to predict power consumption in a similar fashion. We propose a power prediction methodology, Logical Power (LP), compatible with LE that breaks down power consumption into dynamic, static, and short-circuit com- ponents with linear equations dependent on h. This would allow a compact and efficient way to characterize a gate that scales with its environment, as well as to allow designers optimizing with LE to consider not only the speed ramifications of individual gate sizings but power as well. For instance given a target path delay higher than the theoretical mini- mum predicted by LE, sizings could be chosen with LE and LP that minimize power that still result in meeting the target delay. The other major contribution of this work is a new short-circuit power measurement technique for simulation that more accurately distinguishes between short-circuit and the parasitic portions of dynamic power in total active power dissipation than all known tech- niques.

Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.