Chim, Fu Shing. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 79-82). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Background --- p.4 / Chapter 2.1 --- ATPG-Based Rewiring - REWIRE --- p.5 / Chapter 2.2 --- Graph-Based Rewiring - GBAW --- p.7 / Chapter 3 --- Characteristics of Rewiring Algorithms --- p.10 / Chapter 3.1 --- Comparsion between GBAW and REWIRE --- p.10 / Chapter 3.2 --- Problem Definition and Motivation --- p.11 / Chapter 4 --- Expanding Pattern Library --- p.14 / Chapter 4.1 --- Optimizing GBAW's Pattern Library --- p.14 / Chapter 4.2 --- Reduced Function Set for Gates within Patterns --- p.15 / Chapter 4.3 --- Rewiring with Multiple-Input Gates --- p.15 / Chapter 4.4 --- Experiment with GBAW Rewiring --- p.18 / Chapter 4.4.1 --- Experimental Results --- p.18 / Chapter 4.4.2 --- Discussion --- p.19 / Chapter 4.5 --- Experiment with Multi-way GBAW Partitioning --- p.21 / Chapter 4.5.1 --- Experimental Results --- p.22 / Chapter 4.5.2 --- Discussion --- p.24 / Chapter 4.6 --- Summary --- p.24 / Chapter 5 --- Circuit Structure for Rewiring --- p.26 / Chapter 5.1 --- Common Circuit Structure in GBAW Patterns --- p.26 / Chapter 5.2 --- Single Fanout Chains and Reconverging Alternative Wires for REWIRE --- p.28 / Chapter 5.3 --- Successive Rewiring --- p.31 / Chapter 5.4 --- Summary --- p.33 / Chapter 6 --- Chain-Based Rewiring Approach --- p.35 / Chapter 6.1 --- Single Fanout Chains in Graph-Based Rewiring --- p.35 / Chapter 6.2 --- Chain-Based Rewiring Approach --- p.36 / Chapter 6.3 --- Experimental Results --- p.40 / Chapter 6.4 --- Discussion --- p.41 / Chapter 6.5 --- Summary --- p.43 / Chapter 7 --- Hybrid Rewiring Framework --- p.44 / Chapter 7.1 --- Limit of Static Approaches --- p.44 / Chapter 7.2 --- Analyzing Framework of Dynamic Rewiring --- p.45 / Chapter 7.3 --- Techniques for Redundancy Identification --- p.47 / Chapter 8 --- Hybrid Chain-Based Rewiring Approach --- p.53 / Chapter 8.1 --- Hybrid Rewiring Framework --- p.53 / Chapter 8.1.1 --- Chain-Based Preliminary Target Wire Filtering --- p.55 / Chapter 8.1.2 --- Implication-Based Candidate Wire Generation --- p.55 / Chapter 8.1.3 --- Fast Redundancy Identification --- p.57 / Chapter 8.2 --- Uncontrollability and Controlling-Value Paths --- p.58 / Chapter 8.3 --- HYBRID - An Implementation of Our Framework --- p.61 / Chapter 8.4 --- Experimental Results --- p.63 / Chapter 8.5 --- Discussion --- p.65 / Chapter 8.6 --- Summary --- p.67 / Chapter 9 --- Rewiring Coupled FPGA Technology Mapping --- p.68 / Chapter 9.1 --- FPGA Technology Mapping --- p.68 / Chapter 9.2 --- Rewiring Coupled FPGA Technology Mapping --- p.70 / Chapter 9.2.1 --- Rewiring-based Logic Level Reduction --- p.71 / Chapter 9.2.2 --- Incremental Logic Resynthesis (ILR) Area Minimization --- p.71 / Chapter 9.3 --- Experimental Results --- p.72 / Chapter 9.4 --- Discussion --- p.73 / Chapter 9.5 --- Summary --- p.75 / Chapter 10 --- Conclusion and Future Works --- p.76 / Bibliography --- p.79

Spectral methods have been used for many applications in digital logic design, digital signal processing and telecommunications. In digital logic design they are implemented for testing of logical networks, multiplexer-based logic synthesis, signal processing, image processing and pattern analysis. New developments of more efficient algorithms for spectral transformations (Rademacher-Walsh, Generalized Reed-Muller, Adding, Arithmetic, multiple-valued Walsh and multiple-valued Generalized Reed- Muller) their implementation and applications will be described.

Some techniques are presented to permit the implementation of asynchronous sequential circuits using standard flip-flops. An algorithm is presented for the RS flip-flop, and it is shown that any flow table may be realized using the algorithm (the flow table is assumed to be realizable using standard logic gates). The approach is shown to be directly applicable to synchronous circuits, and transition flip-flops (JK, D, and T) are analyzed using the ideas developed. Constraints are derived for the flow tables to meet to be realizable using transition flip-flops in asynchronous situations, and upper and lower bounds on the number of transition flip-flops required to implement a given flow table are stated.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 195-204). Available also in a digital version from Dissertation Abstracts.

No description available.

Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 97-99). Also available in electronic format on the Internet.

Thesis (M.S.)--Rochester Institute of Technology, 1995. / Typescript. Bibliography: leaf 55.

Thesis (M. Eng.)--Carleton University, 1988. / Also available in electronic format on the Internet.

The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophisticated logic design tools. In the beginning of the eighties the research in logic design was concentrated on the development of fast two-level AND-OR logic minimizers like the well known ESPRESSO. However, most logic functions have a smaller and often faster circuit realization as a multi-level circuit. Thus, synthesis tools emerged for the minimization of the circuit area in a multi-level realization. Most of these synthesis tools are based on the "unate paradigm". Therefore, the synthesis methods are only advantageous for functions having a minimal circuit realization based on AND-OR gates. However, many common functions have a minmal circuit realization having a mix of AND, OR and EXOR gates like counters, adders, multipliers, and parity generators. Therefore, the design of such functions with synthesis tools based on the "unated paradigm" is very inefficient. Circuits incorporating the EXOR gate have received less attention than AND-OR circuits because the EXOR gate was perceived as slower and larger in terms of its circuit realization than the AND and the OR gate. However, the upcoming of Field Programmable Gate Arrays (FPGAs) like the Xilinx Table-Look-Up (TLU) architecture the Actel ACTâ„¢ series and the CLi 6000 series from Concurrent Logic, which allow the realization of the EXOR gate with the same speed and circuit cost as the AND and OR gate, eliminates the disadvantages of the EXOR gate over the AND and OR gate. Thus, there is a strong need for logic synthesis tools that take advantage of EXOR gates. The mapping to the new FPGAs recently obtained an increased interest. The developed synthesis algorithms for FPGAs are based on the mapping and restructuring of the Directed Acyclic Graph (DAG) representation of the logic function. Even though the new FPGAs allow the realization of the EXOR gate without any speed and circuit size penalty in comparison to the AND and OR gate, the synthesis methods have been based on the "unate paradigm". To overcome the disadvantages of the current logic synthesis tools with respect to (nearly) linear functions and FPGA synthesis, this dissertation introduces an extended theory of spectral methods for multiple-valued input, incompletely specified binary output logic. The spectral methods have not been popular in logic synthesis because of their four major drawbacks: (1) the computational complexity, especially if no Fast Transform exists, (2) the memory requirement to store the function in the necessary minterm representation, (3) they cannot take efficiently advantage of incompletely specified functions, (4) suitable only for few applications in logic synthesis. To overcome the two last stated drawbacks, this dissertation introduces the T spectrum. The T spectrum separates the information obtained for the specified and not specified parts of the underlying function. Thus, it is possible to determine directly the contribution of the specified and the not specified part of the function to a single spectral coefficient. Moreover, the T spectrum is an extension of the known spectra like Walshtype, Adding, Arithmetic, and Reed-Muller spectra to any orthogonal and nonorthogonal transform describing logic functions. Thus, transforms can be constructed that describe certain gate structures, as for example the realizable functions of a FPGA macrocell. This allows the development of special synthesis algorithms for the different types of FPGA architectures. As an exemplification of this method, a complete multi-level synthesis algorithm is introduced for the circuit realization with multiplexer modules, which form the basic macrocell of the Actel ACfâ„¢ FPGA series. Additionally, this dissertation presents the classification of the applications of spectral methods in logic synthesis into three categories: (1) The decomposition of logic functions based on the information obtained by the computation of a single spectrum. As an example the linearization procedure developed by Karpowsky is generalized to incompletely specified multi-output Boolean functions. The linearization procedure is based on the computation of the Rademacher-Walsh spectrum with a following decomposition of the underlying function based on high value spectral coefficients. (2) The circuit realization of a logic function based on the repetitive application of (1). This synthesis method is exemplified by an multi-level synthesis algorithm for multiplexer gates. (3) The realization of a logic function as an AND-EXOR circuit based on a GF 2 (Galois Field (2)) spectrum. The GF 2 transforms exhibit the property that they describe a realization of the underlying function as a two-level AND-EXOR circuit. The Multiple-Valued Input Kronecker Reed-Muller (MIKRM) form is introduced as an application of GF 2 transforms. To overcome the drawbacks of spectral methods concerning the computational complexity and high memory requirements, this dissertation presents a computation method for spectra from disjoint representations. The introduced application of the disjoint cube representation and the Ordered Decision Diagrams for the computation of spectra proves to be an ideal concept. Thus, this dissertation presents general synthesis methods based on new spectral methods that overcome the deficiencies of current logic synthesis methods with respect to the synthesis for FPGAs as well as the computational complexity and memory requirements of spectral methods.

Paper is one of the elements used in our everyday life under its different forms; from the office use, newspapers, books, post-it, different packaging… it is ever present. The mass production of paper is made possible today by the industrial paper mill. One of a key component affecting the quality of the paper is the forming fabric used as a filter in the preliminary stages of paper manufacturing. The TCR Transcent is such machine used to produce the forming fabric and TEXO-AB assures two third of the world production of the machine. Given the ever increasing customer demand, machine variants and technological need, it is imperial for TEXO-AB to implement a time-efficient and responsive design system. This is made possible by shifting from traditional design to a logic based parametric design. The TCR loom model provided by the method followed in this report allows among other benefit a reduction of up to 28% in the time taken to design a new machine while still attending to the customization element providing a unique machine for every customer. The use of the model will afford designers more time to focus on other essential tasks, schemes and strive toward continuous improvement in terms of quality and technology.