The current trend of ever larger clusters and data centers has coincided with a dramatic increase in the cost and
power of these installations. While many efficiency improvements have focused on processor power and cooling costs,
reducing the cost and power consumption of high-performance memory has mostly been overlooked. This thesis proposes
a new address translation model called Dynamic Partitioned Global Address Space (DPGAS) that extends the ideas of
NUMA and software-based approaches to create a high-performance hardware model that can be used to reduce the overall cost and power of memory in larger server installations. A memory model and hardware implementation of DPGAS is developed, and simulations of memory-intensive workloads are used to show potential cost and power reductions when DPGAS is integrated into a server environment.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/26467 |
| Date | 19 November 2008 |
| Creators | Young, Jeffrey |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Thesis |
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