Non traduit / The introduction of nanometer technologies, has allowed the semiconductor industry to create nanoscale devices in combination with gigascale complexity. However, new technologies bring with them new challenges. In the era of large systems embedded in a single System-On-Chip and fabricated in continuously shrinking technologies, it is important to test and ensure fault-free operation of the whole system. The cost involved in semiconductor test has been steadily growing and testing techniques for integrated circuits are today facing many exciting and complex challenges. Although important advances have been made, existing test solutions are still unable to exhaustively cover all types of defects in advanced technology nodes. Consequently, innovative solutions are required to cope with new failure mechanisms under the constraints of higher density and complexity, cost and time to market pressure, product quality level and usage of low cost test equipment.The work of this thesis is focused on the development of silicon test and characterization methodologies that aid in the accurate detection and resolution of issues that may arise due to variability, manufacturing defects, wear-out or interference. A wide spectrum of these challenges has been addressed from a test perspective to ensure that the availability of effective test solutions does not become a bottleneck in the path towards further scaling. Additionally the advances and innovations introduced in the myriad domains of electronic design, reliability management, manufacturing process improvements etc. that call for the development of advanced, modular and agile test methodologies have been effectively covered within the scope of this work.This thesis presents the significant contributions made for enabling resolution of state of the art industrial test challenges via the design and implementation of novel test strategies (targeting the 28nm FDSOI technology node) for:•Detection & diagnosis of timing faults in standard cells.•Analysis of Setup and Hold margins within silicon.•Verification & reliability analysis of innovative test structures.•Analysis of on-chip self heating.•Enabling characterization and performance evaluation of high speed digital IPs.
| Identifer | oai:union.ndltd.org:theses.fr/2016MONTT285 |
| Date | 05 July 2016 |
| Creators | Patel, Darayus Adil |
| Contributors | Montpellier, Girard, Patrick |
| Source Sets | Dépôt national des thèses électroniques françaises |
| Language | English |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation, Text |
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