In this dissertation, we implement efficient lock-based synchronization by
a novel, high performance, simple and scalable hardware technique and
associated software for a target shared-memory multiprocessor
System-on-a-Chip (SoC). The custom hardware part of our solution is
provided in the form of an intellectual property (IP) hardware unit which
we call the SoC Lock Cache (SoCLC). SoCLC provides effective lock hand-off
by reducing on-chip memory traffic and improving performance in terms of
lock latency, lock delay and bandwidth consumption. The proposed solution
is independent from the memory hierarchy, cache protocol and the processor
architectures used in the SoC, which enables easily applicable
implementations of the SoCLC (e.g., as a reconfigurable or partially/fully
custom logic), and which distinguishes SoCLC from previous approaches.
Furthermore, the SoCLC mechanism has been extended to support priority
inheritance with an immediate priority ceiling protocol (IPCP) implemented
in hardware, which enhances the hard real-time performance of the system.
Our experimental results in a four-processor SoC indicate that SoCLC can
achieve up to 37% overall speedup over spin-lock and up to 48% overall
speedup over MCS for a microbenchmark with false sharing. The priority
inheritance implemented as part of the SoCLC hardware, on the other hand,
achieves 1.43X speedup in overall execution time of a robot application
when compared to the priority inheritance implementation under the
Atalanta real-time operating system. Furthermore, it has been shown that
with the IPCP mechanism integrated into the SoCLC, all of the tasks of the
robot application could meet their deadlines (e.g., a high priority task
with 250us worst case response time could complete its execution in 93us
with SoCLC, however the same task missed its deadline by completing its
execution in 283us without SoCLC). Therefore, with IPCP support, our
solution can provide better real-time guarantees for real-time systems.
To automate SoCLC design, we have also developed an SoCLC-generator tool,
PARLAK, that generates user specified configurations of a custom SoCLC. We
used PARLAK to generate SoCLCs from a version for two processors with 32
lock variables occupying 2,520 gates up to a version for fourteen
processors with 256 lock variables occupying 78,240 gates.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/5253 |
| Date | 12 April 2004 |
| Creators | Akgul, Bilge Ebru Saglam |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Language | en_US |
| Detected Language | English |
| Type | Dissertation |
| Format | 704447 bytes, application/pdf |
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