Wong Fai-leung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 86-89). / Abstracts in English and Chinese. / ABSTRACT --- p.II / 摘要 --- p.III / ACKNOWLEDGMENT --- p.IV / TABLE OF CONTENTS --- p.V / TABLE OF FIGURES --- p.VII / Chapter 1 --- INTRODUCTION --- p.1 / Chapter 2 --- BASIC THEORY OF BRANCH LINE COUPLER --- p.4 / Chapter 2.1 --- Four-port network --- p.4 / Chapter 2.2 --- Even-odd mode analysis --- p.5 / Chapter 2.2.1 --- Even mode excitation --- p.6 / Chapter 2.2.2 --- Odd mode excitation --- p.7 / Chapter 2.2.3 --- Mathematical analysis --- p.9 / Chapter 2.3 --- Simulation results --- p.12 / Chapter 3 --- REVIEW OF ADVANCED BRANCH LINE COUPLER DESIGNS --- p.15 / Chapter 3.1 --- Broad-band uniplanar branch-line design --- p.15 / Chapter 3.2 --- Compact branch-line couplers using slow-wave structure --- p.17 / Chapter 3.3 --- Miniature branch-line coupler using eight two-step stubs --- p.18 / Chapter 3.4 --- Wide band lumped-element 3-dB quadrature coupler --- p.20 / Chapter 3.5 --- Dual band branch line coupler design using left-handed transmission lines --- p.22 / Chapter 4 --- DESIGN THEORY OF DUAL BAND BRANCH LINE COUPLERS --- p.24 / Chapter 4.1 --- design 1 - dual band branch line coupler with sub-optimum performance --- p.25 / Chapter 4.1.1 --- Analysis and design --- p.26 / Chapter 4.1.2 --- Size comparison --- p.30 / Chapter 4.2 --- Design 2 - dual band branch line coupler using shunt stubs --- p.34 / Chapter 4.2.1 --- Analysis and design --- p.35 / Chapter 4.2.2 --- Size comparison --- p.41 / Chapter 5 --- SIMULATION VERIFICATION --- p.44 / Chapter 5.1 --- Design 1 --- p.44 / Chapter 5.1.1 --- Schematic simulation --- p.45 / Chapter 5.1.2 --- Schematic simulation with line width deviation --- p.48 / Chapter 5.1.3 --- Schematic simulation with junction discontinuity --- p.54 / Chapter 5.2 --- Design 2 --- p.58 / Chapter 5.2.1 --- Schematic simulation --- p.58 / Chapter 5.2.2 --- Schematic simulation with line width deviation --- p.62 / Chapter 5.2.3 --- Schematic simulation with junction discontinuity --- p.68 / Chapter 6 --- CIRCUIT IMPLEMENTATION AND CHARACTERIZATION --- p.74 / Chapter 6.1 --- Design 1 --- p.74 / Chapter 6.1.1 --- Circuit fabrication --- p.74 / Chapter 6.1.2 --- Measurement results --- p.75 / Chapter 6.2 --- Design 2 --- p.78 / Chapter 6.2.1 --- Circuit fabrication --- p.78 / Chapter 6.2.2 --- Measurement results --- p.79 / Chapter 7 --- CONCLUSIONS --- p.83 / Chapter 8 --- RECOMMENDATIONS FOR FUTURE WORK --- p.85 / Chapter 9 --- REFERENCES --- p.86 / Chapter 10 --- AUTHOR'S PUBLICATIONS --- p.90

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The work presented in this thesis covers an investigation into the use of metal nanoclusters in nanoelectronics design. Initial studies explored the interactions of the dodecanethiol passivated gold nanocluster, held in solution with toluene, and the native oxide covered silicon surface. Deposition of the clusters is achieved by pipetting u-litre quantities of the solution onto the surface, and allowing the solvent to evaporate leaving the clusters as residue. Patterning of the surface with micron scale photoresist structures prior to cluster exposure, led to the selective aggregation of cluster deposits along the resist boundaries. An extension of this technique, examined the flow of the cluster solution along photoresist structures which extended beyond the solution droplet. Investigation into the electronic properties of nanocluster arrays generated non-linear current-voltage curves, which are explained in terms of two very simple models. These results cast doubt over the suitability of the lateral approach to nanocluster device fabrication, and led to the exploration of vertical device design. Vertical devices, based around -50nm diameter silicon nanopillars with nanoc1usters on top, afford the necessary level of control over all aspects of nanocluster positioning; deposition of a single cluster layer is confined laterally to the pillar cross-section. Initial results of vertical device fabrication, show the considerable promise of this approach to cluster based electronic systems.

In this dissertation, we implement efficient lock-based synchronization by a novel, high performance, simple and scalable hardware technique and associated software for a target shared-memory multiprocessor System-on-a-Chip (SoC). The custom hardware part of our solution is provided in the form of an intellectual property (IP) hardware unit which we call the SoC Lock Cache (SoCLC). SoCLC provides effective lock hand-off by reducing on-chip memory traffic and improving performance in terms of lock latency, lock delay and bandwidth consumption. The proposed solution is independent from the memory hierarchy, cache protocol and the processor architectures used in the SoC, which enables easily applicable implementations of the SoCLC (e.g., as a reconfigurable or partially/fully custom logic), and which distinguishes SoCLC from previous approaches. Furthermore, the SoCLC mechanism has been extended to support priority inheritance with an immediate priority ceiling protocol (IPCP) implemented in hardware, which enhances the hard real-time performance of the system. Our experimental results in a four-processor SoC indicate that SoCLC can achieve up to 37% overall speedup over spin-lock and up to 48% overall speedup over MCS for a microbenchmark with false sharing. The priority inheritance implemented as part of the SoCLC hardware, on the other hand, achieves 1.43X speedup in overall execution time of a robot application when compared to the priority inheritance implementation under the Atalanta real-time operating system. Furthermore, it has been shown that with the IPCP mechanism integrated into the SoCLC, all of the tasks of the robot application could meet their deadlines (e.g., a high priority task with 250us worst case response time could complete its execution in 93us with SoCLC, however the same task missed its deadline by completing its execution in 283us without SoCLC). Therefore, with IPCP support, our solution can provide better real-time guarantees for real-time systems. To automate SoCLC design, we have also developed an SoCLC-generator tool, PARLAK, that generates user specified configurations of a custom SoCLC. We used PARLAK to generate SoCLCs from a version for two processors with 32 lock variables occupying 2,520 gates up to a version for fourteen processors with 256 lock variables occupying 78,240 gates.

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.

Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.