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Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits

This thesis proposes a synthesis methodology which is capable of fault-tolerance and deadlock-free for constructing a custom NoC topology in 3D ICs. In this thesis, the processors and their communications can be synthesized simultaneously in the system-level floorplanning with fault tolerant consideration, called 3D-NoC-FT. Experimental results show that the pro-posed 3D-NoC-FT produces custom 3D NoCs with lower power dissipation than previous works. This method is also more scalable, which makes it ideal for complicated 3D NoC de-signs. Compared with the previous 3D NoC work (3D-SAL-FP) without link fault tolerance, our fault tolerant method outperforms on the average the power dissipation by 1.67X with rela-tively small overhead of latency by 17% and the number of TSV by 35%, respectively.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0801111-164321
Date01 August 2011
CreatorsZheng, Yi-Xue
ContributorsShen-Fu Hsiao, Shu-Min Li, Chua-Chin Wang, Chung-Nan Lee
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-164321
Rightsuser_define, Copyright information available at source archive

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