In this thesis, we present a new continuously variable high frequency standing wave oscillator
and demonstrate its use in generating the phase locked clock signal of a digital IC.
The ring based standing wave resonant oscillator is implemented with a plurality of wires
connected in a mobius configuration, with a cross coupled inverter pair connected across
the wires. The oscillation frequency can be modulated by coarse and fine tuning. Coarse
modification is achieved by altering the number of wires in the ring that participate in the
oscillation, by driving a digital word to a set of passgates which are connected to each wire
in the ring. Fine tuning of the oscillation frequency is achieved by varying the body bias
voltage of both the PMOS transistors in the cross coupled inverter pair which sustains the
oscillations in the resonant ring. We validated our PLL design in a 90nm process technology.
3D parasitic RLCs for our oscillator ring were extracted with skin effect accounted for.
Our PLL provides a frequency locking range from 6 GHz to 9 GHz, with a center frequency
of 7.5 GHz. The oscillator alone consumes about 25 mW of power, and the complete PLL
consumes a power of 28.5 mW. The observed jitter of the PLL is 2.56 percent. These numbers
are significant improvements over the prior art in standing wave based PLLs.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2010-08-8546 |
| Date | 2010 August 1900 |
| Creators | Karkala, Vinay |
| Contributors | Khatri, Sunil P. |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | thesis, text |
| Format | application/pdf |
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