This thesis proposes a synthesis methodology which is capable of fault-tolerance and deadlock-free for constructing a custom NoC topology in 3D ICs. In this thesis, the processors and their communications can be synthesized simultaneously in the system-level floorplanning with fault tolerant consideration, called 3D-NoC-FT. Experimental results show that the pro-posed 3D-NoC-FT produces custom 3D NoCs with lower power dissipation than previous works. This method is also more scalable, which makes it ideal for complicated 3D NoC de-signs. Compared with the previous 3D NoC work (3D-SAL-FP) without link fault tolerance, our fault tolerant method outperforms on the average the power dissipation by 1.67X with rela-tively small overhead of latency by 17% and the number of TSV by 35%, respectively.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0801111-164321 |
| Date | 01 August 2011 |
| Creators | Zheng, Yi-Xue |
| Contributors | Shen-Fu Hsiao, Shu-Min Li, Chua-Chin Wang, Chung-Nan Lee |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-164321 |
| Rights | user_define, Copyright information available at source archive |
Page generated in 0.0025 seconds