The objective of this research work is to develop an efficient methodology for chip-package
cosimulation. In the traditional design flow, the integrated circuit (IC) is first designed
followed by the package design. The disadvantage of the conventional sequential design
flow is that if there are problems with signal and power integrity after the integration of
the IC and the package, it is expensive and time consuming to go back and change the
IC layout for a different input/output (IO) pad assignment. To overcome this limitation,
a concurrent design flow, where both the IC and the package are designed together, has
been recommended by researchers to obtain a fast design closure. The techniques from this
research work will enable multiscale cosimulation of the chip and the package making the
concurrent design flow paradigm possible.
Traditional time-domain techniques, such as the finite-difference time-domain method,
are limited by the Courant condition and are not suitable for chip-package cosimulation. The
Courant condition gives an upper bound on the time step that can be used to obtain stable
simulation results. The smaller the mesh dimension the smaller is the Courant time step. In
the case of chip-package cosimulation the on-chip structures require a fine mesh, which can
make the time step prohibitively small. An unconditionally stable scheme using Laguerre
polynomials has been recommended for chip-package cosimulation. Prior limitations in
this method have been overcome in this research work. The enhanced transient simulation
scheme using Laguerre polynomials has been named SLeEC, which stands for simulation
using Laguerre equivalent circuit. A full-wave EM simulator has been developed using the
SLeEC methodology.
A scheme for efficient use of full-wave solver for chip-package cosimulation has been
proposed. Simulation of the entire chip-package structure using a full-wave solver could be
a memory and time-intensive operation. A more efficient way is to separate the chip-package
structure into the chip, the package signal-delivery network, and the package power-delivery
network; use a full-wave solver to simulate each of these smaller subblocks and integrate
them together in the following step, before a final simulation is done on the integrated
network. Examples have been presented that illustrate the technique.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/24705 |
| Date | 19 May 2008 |
| Creators | Srinivasan, Gopikrishna |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Dissertation |
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