To increase the productivity of electronic systems design we offer to use UML – the standard specification language of high level systems. The higher level of abstraction and automatic design methods could decrease a gap of hardware design. We offer to use UML class diagrams for the specification of electronic systems structure and UML state diagrams to specify the behavior of electronic systems. We introduce metamodels which describe mapping between UML class and state diagrams and hardware description languages (VHDL, SystemC), as the possible realization of ideas we introduced earlier. Also we provide code generator which translates notations of UML class and state diagrams to VHDL and SystemC languages.
| Identifer | oai:union.ndltd.org:LABT_ETD/oai:elaba.lt:LT-eLABa-0001:E.02~2006~D_20060605_200924-56976 |
| Date | 05 June 2006 |
| Creators | Aklys, Andrius |
| Contributors | Maciulevičius, Stasys, Pranevičius, Henrikas, Barauskas, Rimantas, Mockus, Jonas, Plėštys, Rimantas, Ziberkas, Giedrius, Jasinevičius, Raimundas, Damaševičius, Robertas, Telksnys, Laimutis, Kaunas University of Technology |
| Publisher | Lithuanian Academic Libraries Network (LABT), Kaunas University of Technology |
| Source Sets | Lithuanian ETD submission system |
| Language | Lithuanian |
| Detected Language | English |
| Type | Master thesis |
| Format | application/pdf |
| Source | http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2006~D_20060605_200924-56976 |
| Rights | Unrestricted |
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