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Bus Interface Design Between Different Clock Domains and Its Application to OpenGL-ES 2.0 3D Graphics Systems

Asynchronous bus interface units to AMBA AHB are designed so that an OpenGL ES 2.0 vertex shader can communicate with other hardware units via AHB bus under different working frequencies. The first design is to directly implement an asynchronous AHB wrapper for the vertex shader. The other two designs are based on Open Core Protocol (OCP) to allow for more flexibility. The hardware intellectual property (IP), vertex shader in this thesis, to OCP asynchronous unit is designed so that the IP can be developed independently with different bus protocols as long as the OCP-to-bus interface is provided for a particular bus protocol. With the help of asynchronous IP-to-OCP and OCP-to-AHB interface units, the vertex shader IP can operate at different frequencies from the AHB bus. Furthermore, the same vertex shader (VS) can be connected to other bus protocol (such as AXI) of different frequencies if the OCP-to-AXI interface is provided because the the asynchronous VS-to-OCP have been designed in this thesis.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0726111-142933
Date26 July 2011
CreatorsLin, Chi-Guang
ContributorsMing-Chih Chen, Ming-Chih Chen, Chuen-Yau Chen, Shen-Fu Hsiao, Jih-ching Chiu
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-142933
Rightsoff_campus_withheld, Copyright information available at source archive

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