In this thesis, we present a new register-transfer level (RTL) test generation method that makes use of two coverage metrics, Branch Coverage, and Mutation Coverage across two stages, to cover hard-to-reach points previously unreached. We start with a preprocessing stage by converting the RTL source to a C++ equivalent using a modified Verilator, which also automatically creates mutants and the corresponding mutated C++ design, based on arithmetic, logical and relational operators during conversion. With the help of extracted Data Dependency and Control Flow Graphs, in every <golden, mutation> pair, branches containing variables dependent on the mutated statement are instrumented to track them. The first stage uses Evolutionary algorithms with Ant Colony Optimization to generate test vectors with mutation coverage as the metric. Two new filtering techniques are also proposed which optimize the first stage by eliminating the need for generating tests for redundant mutants. The next stage is the original BEACON which now takes the generated mutation test vectors as the initial population unlike random vectors, and output final test vectors. These test vectors succeed in improving the coverage up to 70%, compared to the previous approaches for most of the ITC99 benchmarks. With the application of filtering techniques, we also observed a speedup by 85% in the test generation runtime and also up to 78% reduction in test vector size when compared with those generated by the previous techniques. / MS / In the recent years, Verification has become one of the major bottlenecks in integrated circuit design process, which is exacerbated by the increasing design complexities today. Today designers start the design process by abstracting the initial design in a manner similar to software programming language using a higher abstraction language called Hardware Descriptive Language(HDL). Hence, an HDL based design also contains a number of case statements and if-else statements, also called branches, similar to a software design. Branches indicate decision points in the design and high branch coverage based tests can give us an assurance that the design is properly exercised as compared to those given by randomly generated tests. In this thesis, we introduce a new test generation methodology which generates tests using the help of user introduced mutants to ensure higher branch coverage. Mutation testing is similar to a fault testing method, in which an error or a fault is deliberately introduced into the design and we check if the tests generated are able to detect the fault. An important property of a mutant is that: when a mutant is applied and if the mutated part of the design is exercised by the given test suite, then the following data and control flow path taken can be different from that taken on the original design. This important property along with proper guidance is used in our work to reach some branches which are difficult to cover by random test vectors, and this is the main basis of this thesis. Applying this method, we observed that the branch coverage increased with a decrease in test generation runtime and test vector length when compared to previously proposed techniques.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/96581 |
| Date | 02 August 2018 |
| Creators | Bansal, Kunal |
| Contributors | Electrical and Computer Engineering, Hsiao, Michael S., Zeng, Haibo, Abbott, A. Lynn |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis |
| Format | ETD, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
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