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Previous issue date: 2012-03-30 / It bet on the next generation of computers as architecture with multiple processors and/or
multicore processors. In this sense there are challenges related to features interconnection, operating
frequency, the area on chip, power dissipation, performance and programmability. The mechanism of
interconnection and communication it was considered ideal for this type of architecture are the
networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip
communication is accomplished by transmitting packets that carry data and instructions that
represent requests and responses between the processing elements interconnected by the network.
The transmission of packets is accomplished as in a pipeline between the routers in the network, from
source to destination of the communication, even allowing simultaneous communications between
pairs of different sources and destinations. From this fact, it is proposed to transform the entire
infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and
storage, in a parallel processing system for high performance. In this proposal, the packages are
formed by instructions and data that represent the applications, which are executed on routers as
well as they are transmitted, using the pipeline and parallel communication transmissions. In
contrast, traditional processors are not used, but only single cores that control the access to memory.
An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an
own programming model and a routing algorithm that guarantees the execution of all instructions in
the packets, preventing situations of deadlock, livelock and starvation. This architecture provides
mechanisms for input and output, interruption and operating system support. As proof of concept
was developed a programming environment and a simulator for this architecture in SystemC, which
allows configuration of various parameters and to obtain several results to evaluate it / Aposta-se na pr?xima gera??o de computadores como sendo de arquitetura com m?ltiplos
processadores e/ou processadores com v?rios n?cleos. Neste sentido h? desafios relacionados aos
mecanismos de interconex?o, frequ?ncia de opera??o, ?rea ocupada em chip, pot?ncia dissipada,
programabilidade e desempenho. O mecanismo de interconex?o e comunica??o considerado ideal
para esse tipo de arquitetura s?o as redes em chip, pela escalabilidade, paralelismo intr?nseco e
reusabilidade. A comunica??o nas redes em chip ? realizada atrav?s da transmiss?o de pacotes que
carregam dados e instru??es que representam requisi??es e respostas entre os elementos
processadores interligados pela rede. A transmiss?o desses pacotes acontece como em um pipeline
entre os roteadores da rede, da origem at? o destino da comunica??o, permitindo inclusive
comunica??es simult?neas entre pares de origem e destinos diferentes. Partindo desse fato, prop?ese
transformar toda a infraestrutura de comunica??o de uma rede em chip, aproveitando os
mecanismos de roteamento, arbitragem e memoriza??o em um sistema de processamento paralelo
de alto desempenho. Nessa proposta os pacotes s?o formados por instru??es e dados que
representam as aplica??es, os quais s?o executados nos roteadores enquanto s?o transmitidos,
aproveitando o pipeline das transmiss?es e a comunica??o paralela. Em contrapartida, n?o s?o
utilizados processadores tradicionais, mas apenas n?cleos simples que controlam o acesso a
mem?ria. Uma implementa??o dessa ideia ? a arquitetura intitulada IPNoSys (Integrated Processing
NoC System), que conta com um modelo de programa??o pr?prio e um algoritmo de roteamento que
garante a execu??o de todas as instru??es presentes nos pacotes, prevenindo situa??es de deadlock,
livelock e starvation. Essa arquitetura apresenta mecanismos de entrada e sa?da, interrup??o e
suporte ao sistema operacional. Como prova de conceito foi desenvolvido um ambiente de
programa??o e simula??o para esta arquitetura em SystemC, o qual permite a configura??o de v?rios
par?metros da arquitetura e obten??o dos resultados para avalia??o da mesma
| Identifer | oai:union.ndltd.org:IBICT/oai:repositorio.ufrn.br:123456789/17948 |
| Date | 30 March 2012 |
| Creators | Ara?jo, S?lvio Roberto Fernandes de |
| Contributors | CPF:43728090425, http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2, Susin, Altamiro Amadeu, CPF:05799830059, http://lattes.cnpq.br/6766389440522985, Zeferino, Cesar Albenes, CPF:65254856068, http://lattes.cnpq.br/9888386354516064, D?harbe, David Boris Paul, CPF:00809085437, http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4768856U5, Kreutz, M?rcio Eduardo, CPF:58434296049, http://lattes.cnpq.br/6374279398246756, Silva, Ivan Saraiva |
| Publisher | Universidade Federal do Rio Grande do Norte, Programa de P?s-Gradua??o em Sistemas e Computa??o, UFRN, BR, Ci?ncia da Computa??o |
| Source Sets | IBICT Brazilian ETDs |
| Language | Portuguese |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, info:eu-repo/semantics/doctoralThesis |
| Format | application/pdf |
| Source | reponame:Repositório Institucional da UFRN, instname:Universidade Federal do Rio Grande do Norte, instacron:UFRN |
| Rights | info:eu-repo/semantics/openAccess |
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