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Characterization of Multi-Gate Partially-Depleted SOI MOSFET with MESA Isolation

Abstract
In this thesis, a Multi-gate PD SOI Device is realized. The inverse narrow channel effect of the device is also studied.
In the Multi-gate PD SOI structure, it has three-surface gate on the silicon MESA Island, which can promote the device performance. However, for eliminating the abnormal corner leakage current in the MESA Island, the process of rounded corner is used. In order to overcome the floating body effect, we use the Schottky body contact. According to the 3-D DAVINCI device simulation and the measurement results, the Multi-gate PD SOI device presents the excellent characteristics: low threshold voltage, low subthreshold factor and high breakdown voltage. In addition, comparing the Multi-gate device with that of the conventional one, the excess drain current gain is observed.
In order to understand the behavior of INCE in Multi-gate PD SOI Device in depth, we use the concept of overlap depletion region to derive the expressions of threshold voltage shift. Owing to the device has rounded corner, we also study the rounded corner effect in the model formulation. Comparing calculation with that of the experiment one, the calculation shows agreement with the experiments.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0720101-205542
Date20 July 2001
CreatorsHuang, Kuo-Ying
ContributorsChia-Hsiung Kao, Jim-Shyan Wang, Yao-Tsung Tsai, Jyi-Tesong Lin
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageEnglish
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0720101-205542
Rightsnot_available, Copyright information available at source archive

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