<p>We are in the midst of a technological revolution (popularly
known as Industrie 4.0 or 4th Industrial Revolution) where our cars are being
equipped with hundreds of sensors that make them safer, homes are becoming
smarter, industry yields are at an all-time high, and internet-of-things is a
reality. This was largely possible due to the developments in communication,
electronics, motor controls, robotics, cyber security, software, efficient
power distribution, etc. One of the major propellants of the 4th Industrial
revolution is the ever-expanding applications of power electronics devices. All
electrical energy will be provided, handled, and consumed through power
electronics devices in the near future. Therefore, the reliability of power
electronics devices will be instrumental in driving future technological
advances. </p>
<p> </p>
<p><br></p><p>A myriad of devices is categorized as power electronics
devices, and in the heart of those devices are the transistors. Although
Silicon-based transistors still dominate the power electronics market, a
paradigm shift towards wide bandgap semiconductors, such as silicon carbide
(SiC), gallium nitride (GaN), beta-gallium oxide etc., is underway. However,
realizing the full potential of these devices demands unconventional design,
layout, and reliability. </p>
<p> </p>
<p>In this thesis, we try to establish a generalized model of
reliability for power and logic transistors. We start by defining a
comprehensive, substrate-, self-heating-, and reliability-aware safe operating
area (SOA) that analytically establishes the optimum and self-consistent
trade-off among breakdown voltage, power consumption, operating frequency, heat
dissipation, and reliability before actual device fabrication. Then we take a
deeper look into the reliability of individual transistors (a beta-gallium
oxide transistor and a Silicon-based LDMOS), to test the predictions by the
safe operating area, using both experiments and simulations. In the beta-gallium
oxide transistor, we studied its implementation in a DC-DC voltage converter
and concluded that the self-heating is a performance bottleneck and suggested
approaches to alleviate it. For the LDMOS transistor, we investigated the hot
carrier degradation (HCD) using experiments and simulations. We established
that the HCD degradation kinetics is universal, and physics is the same as a
classical transistor, despite a complicated geometry. Finally, we studied the correlation between
HCD and radiation in LDMOS used in space shuttles, airplanes, etc., to
determine its lifetime. </p><p><br></p>
<p> </p>
<p>We have holistically analyzed the reliability of power transistors
by extending the theories of logic transistors in this thesis. Therefore, this
thesis takes us a step closer to a generalized reliability model for power
transistors by developing a comprehensive and predictive model for the safe
operating area, encompassing all sources of stresses (e.g., electrical,
thermal, and radiation) it experiences during operation.</p>
| Identifer | oai:union.ndltd.org:purdue.edu/oai:figshare.com:article/17126615 |
| Date | 19 December 2021 |
| Creators | Bikram Kishore Mahajan (11794316) |
| Source Sets | Purdue University |
| Detected Language | English |
| Type | Text, Thesis |
| Rights | CC BY 4.0 |
| Relation | https://figshare.com/articles/thesis/Electro-thermal_and_Radiation_Reliability_of_Power_Transistors_Silicon_to_Wide_Bandgap_Semiconductors/17126615 |
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