The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown was reported and modeled. Physical design parameters that are crucial to backend dielectric reliability were identified. A methodology was proposed for determining chip reliability but combining the insights gathered by modeling the impact of physical design on backend dielectric breakdown.
A methodology to model variation in device parameters and characteristics was proposed. New methods of electrical and physical parameter extraction were proposed. Models that consider systematic and random source of variation in electrical and physical parameters of CMOS devices were proposed, to aid in circuit design and timing analysis.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/41092 |
| Date | 20 May 2011 |
| Creators | Bashir, Muhammad Muqarrab |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Dissertation |
Page generated in 0.0021 seconds