The advent of smart and wearable systems along with their Internet of Things (IoT) applications are driving unparalleled product miniaturization and multifunctional integration with computing, wireless communications, wireless healthcare, security, banking, entertainment, and navigation and others. This evolution is primarily enabled by the integration of multiple technologies such as RF, analog, digital, MEMS, sensors and optics in the same system. Integration of these heterogeneous technologies creates a new need for multiple power supply rails to provide device-specific voltage and current levels. Hence, multiple power converters, each requiring several passive components, are used to create stable power-supplies. However, state-of-art power supplies employ SMD passives that are relatively large, forcing these modules to be placed on the board far from the active IC. This leads to significantly sub-par frequency performance and poses a challenge for ultra-miniaturized and reliable power supplies. Hence, novel packaging technologies that can improve miniaturization, electrical performance and reliability at a relatively low-cost are required to address these challenges. Georgia Tech-PRC proposes 3D integration of passives and actives (3D IPAC) as doubleside thin components on ultra-thin glass substrates with through-package-vias (TPVs) to meet these requirements. This thesis focuses on a comprehensive methodology to demonstrate a 3D IPAC power module, starting with modeling, design, fabrication and characterization to validate 3D integrated ultra-thin inductors and capacitors in ultra-thin substrates. Another key focus of this thesis is to advance building block technologies such as thinfilm inductors and capacitors to achieve the target properties for 3D IPAC integration.
As a first building block technology, advanced capacitor technologies were explored with high-k thinfilm barium strontium titanate dielectrics and lanthanum nickel oxide electrodes as an alternative to Cu, Ni and Pt electrodes for improved performance and cost. The BST capacitors with LNO electrodes resulted in a capacitance density of 20-30 nF/cm2 with leakage as low as nA/nF up to 3 V. A glass-compatible process was developed with crystallization temperatures less than 650 C. These capacitors with thinfilm electrodes and dielectrics can be integrated into ultra-thin interposers and packages. This can help improve the capacitor performance up to the GHz range.
As a next build block, Si-nanowires were studied as high surface area electrodes for high-density capacitors. Analytical modeling was performed to understand the length of the nanowires based on the catalyst size. This modeling study was then extended to understand the cut-off frequency of the capacitors based on the RC time constant. The wires were fabricated using both chemical vapor deposition (CVD) and wet-etch processes. However, it was noticed that the wet-etch process provided more control on the geometry, density and orientation of the nanowires. Si-oxide was thermally grown on the surface of the wires. A capacitance density of 200 nF/mm2 was achieved. It was noticed that the cut-off frequency of such capacitors was limited to the lower kHz range. However, the operating frequency can be improved by simply using a highly conductive Si-substrate.
The second part of the thesis focuses on inductor and capacitor integration on ultra-thin glass substrates for high-frequency power modules using the 3D IPAC approach. Analytical models were used to calculate the required passive component values based on the target frequency, ripple currents and voltages of the power module. Next, a SPICE model was used to optimize the value of the required passives based on the output parasitics. The L and C structures were then modeled using 2.5D method of moments (MOM) approach. The modeling results showed 7-8 X improvement in Q-factor when the structures were fabricated using the 3D IPAC approach relative to those fabricated on the same side of the substrate. A fabrication process flow was designed based on through-via and doubleside metallization with semi-additive patterning (SAP). The components were fabricated as thinfilms on either sides of the substrate and interconnected with through-vias. The LC network was characterized using a two-port vector network analyzer. The results showed low-pass filter response, which matched the design targets of cut-off frequencies upto 100 MHz. This study, therefore, demonstrates advanced thinfilm component technologies for ultra-high frequency power-supply. It also presents, for the first time, a 3D integrated passives and actives (3D IPAC) approach with integrated L and C for power modules.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/53906 |
| Date | 21 September 2015 |
| Creators | Gandhi, Saumya |
| Contributors | Tummala, Rao |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Dissertation |
| Format | application/pdf |
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