The Study of Microstructure Analysis of Pb/Sn And Sn/Ag/Cu Solder Ball in BGA Package.

The advent of smart and wearable systems along with their Internet of Things (IoT) applications are driving unparalleled product miniaturization and multifunctional integration with computing, wireless communications, wireless healthcare, security, banking, entertainment, and navigation and others. This evolution is primarily enabled by the integration of multiple technologies such as RF, analog, digital, MEMS, sensors and optics in the same system. Integration of these heterogeneous technologies creates a new need for multiple power supply rails to provide device-specific voltage and current levels. Hence, multiple power converters, each requiring several passive components, are used to create stable power-supplies. However, state-of-art power supplies employ SMD passives that are relatively large, forcing these modules to be placed on the board far from the active IC. This leads to significantly sub-par frequency performance and poses a challenge for ultra-miniaturized and reliable power supplies. Hence, novel packaging technologies that can improve miniaturization, electrical performance and reliability at a relatively low-cost are required to address these challenges. Georgia Tech-PRC proposes 3D integration of passives and actives (3D IPAC) as doubleside thin components on ultra-thin glass substrates with through-package-vias (TPVs) to meet these requirements. This thesis focuses on a comprehensive methodology to demonstrate a 3D IPAC power module, starting with modeling, design, fabrication and characterization to validate 3D integrated ultra-thin inductors and capacitors in ultra-thin substrates. Another key focus of this thesis is to advance building block technologies such as thinfilm inductors and capacitors to achieve the target properties for 3D IPAC integration. As a first building block technology, advanced capacitor technologies were explored with high-k thinfilm barium strontium titanate dielectrics and lanthanum nickel oxide electrodes as an alternative to Cu, Ni and Pt electrodes for improved performance and cost. The BST capacitors with LNO electrodes resulted in a capacitance density of 20-30 nF/cm2 with leakage as low as nA/nF up to 3 V. A glass-compatible process was developed with crystallization temperatures less than 650 C. These capacitors with thinfilm electrodes and dielectrics can be integrated into ultra-thin interposers and packages. This can help improve the capacitor performance up to the GHz range. As a next build block, Si-nanowires were studied as high surface area electrodes for high-density capacitors. Analytical modeling was performed to understand the length of the nanowires based on the catalyst size. This modeling study was then extended to understand the cut-off frequency of the capacitors based on the RC time constant. The wires were fabricated using both chemical vapor deposition (CVD) and wet-etch processes. However, it was noticed that the wet-etch process provided more control on the geometry, density and orientation of the nanowires. Si-oxide was thermally grown on the surface of the wires. A capacitance density of 200 nF/mm2 was achieved. It was noticed that the cut-off frequency of such capacitors was limited to the lower kHz range. However, the operating frequency can be improved by simply using a highly conductive Si-substrate. The second part of the thesis focuses on inductor and capacitor integration on ultra-thin glass substrates for high-frequency power modules using the 3D IPAC approach. Analytical models were used to calculate the required passive component values based on the target frequency, ripple currents and voltages of the power module. Next, a SPICE model was used to optimize the value of the required passives based on the output parasitics. The L and C structures were then modeled using 2.5D method of moments (MOM) approach. The modeling results showed 7-8 X improvement in Q-factor when the structures were fabricated using the 3D IPAC approach relative to those fabricated on the same side of the substrate. A fabrication process flow was designed based on through-via and doubleside metallization with semi-additive patterning (SAP). The components were fabricated as thinfilms on either sides of the substrate and interconnected with through-vias. The LC network was characterized using a two-port vector network analyzer. The results showed low-pass filter response, which matched the design targets of cut-off frequencies upto 100 MHz. This study, therefore, demonstrates advanced thinfilm component technologies for ultra-high frequency power-supply. It also presents, for the first time, a 3D integrated passives and actives (3D IPAC) approach with integrated L and C for power modules.

In this research, wafer-level flexible input/output interconnection technologies, Mechanically Flexible Interconnects (MFIs), have been developed. First, Au-NiW MFIs with 65 µm vertical elastic range of motion are designed and fabricated. The gold passivation layer is experimentally verified to not only lower the electrical resistance but also significantly extend the life-time of the MFIs. In addition, a photoresist spray-coating based fabrication process is developed to scale the in-line pitch of MFIs from 150 µm to 50 µm. By adding a contact-tip, Au-NiW MFI could realize a rematable assembly on a substrate with uniform pads and a robust assembly on a substrate with 45 µm surface variation. Last but not least, multi-pitch multi-height MFIs (MPMH MFIs) are formed using double-lithography and double-reflow processes, which can realize an MFI array containing MFIs with various heights and various pitches. Using these advanced MFIs, large scale heterogeneous systems which can provide high performance system-level interconnections are demonstrated. For example, the demonstrated 3D interposer stacking enabled by MPMH MFIs is promising to realize a low profile and cavity-free robust stacking system. Moreover, bridged multiinterposer system is developed to address the reticle and yield limitations of realizing a large scale system using current 2.5D integration technologies. The high-bandwidth interconnection available within interposer can be extended by using a silicon chip to bridge adjacent interposers. MFIs assisted thermal isolation is also developed to alleviate thermal coupling in a high-performance 3D stacking system.

Electromigration (EM) and thermomigration (TM) reliability of Pb-free solder joints are emerging as critical concerns in advanced packages. In this study, EM and TM phenomena in Sn-2.5Ag solder joints with thick Cu or thin Ni under-bump metallurgy (UBM) were investigated. A series of EM tests were performed to obtain activation energy (Q) and current density exponent (n), and to understand failure mechanisms. Joule heating was also taken into account. Q and n values were determined as follows: for Cu UBM solders, Q = 1.0 eV and n = 1.5; for Ni UBM solders, Q = 0.9 and n = 2.2. Important factors limiting EM reliability of Pb-free solder joints were found to be UBM dissolution with extensive intermetallic compound (IMC) growth and current crowding. IMC growth without current stressing was found to follow the parabolic growth law whereas linear growth law was observed for Cu₆Sn₅ and Ni₃Sn₄ under high current stressing. For Cu UBM solders, the apparent activation energy for IMC growth was consistent with the activation energy for EM, which supports that EM failure was closely related to IMC growth. In contrast, for Ni UBM solders the apparent activation energy was higher than the EM activation energy. It was suggested that the EM failure in the Ni UBM solders could be associated with more than one mass transport mechanism. The current crowding effect was analyzed with different thicknesses of Ni UBM. It was found that the maximum current density in solder could represent the current density term in Black's equation better than the average current density. FEM studies demonstrated that current crowding was mainly controlled by UBM thickness, metal trace design, and passivation opening diameter. A large temperature gradient of the order of 10³ °C/cm was generated across the sample to induce noticeable TM and to compare its effect against that of EM. TM-induced voiding was observed in Ni UBM solders while UBM dissolution with IMC formation occurred in Cu UBM solders. However, the relative effect of TM was found to be several times smaller than that of EM even at this large temperature gradient. / text

<p dir="ltr">Modeling and simulation play a pivotal role in engineering and research, enabling cost effective solutions for design, manufacturing, and failure analysis, especially where physical testing is infeasible. This work explores numerical methods for multi-scale domains, where structures span diverse length scales, presenting unique challenges in meshing and accuracy. Advanced approaches such as domain decomposition and global-local methods are discussed, with an emphasis on their application in heterogeneous integration (HI) for advanced packaging. HI, which addresses the limitations of Moore’s Law, integrates diverse components into 2.5D and 3D architectures but introduces complex mechanical and thermo-mechanical challenges. This research addresses gaps in multi-scale numerical frameworks, proposing novel methods to handle non-linear physical evolution while maintaining compatibility with existing tools. A non-intrusive global-local inspired methodology that couples the local subdomain back to the global subdomain was implemented to increase the accuracy in non-linear multi-scale simulations involving evolution at local scale. The developed framework was then generalized to solve rate dependent and rate independent phenomenon. The work further extends into numerical methods for design of HI packages as well. Unlike detailed analysis, the design stage analysis prioritizes speed of computation with a first order accuracy of results. This is achieved using machine learning techniques for efficient design space exploration in HI. The study overall aims to advance computational frameworks tailored for accuracy in reliability analysis and speed in design stages, focusing on semiconductors and advanced packaging applications.</p>

<p dir="ltr">Phase evolution mechanisms in micro and nanoscale devices present unique challenges due to distinct behaviors at reduced scales due to surface diffusion. In solder microbumps with size less than 100 micron, surface diffusion causes voiding in the solder bump accompanied by intermetallic formation at the copper sidewall. As the scale and pitch of the interconnects in electronic packages decrease, there is a need to fabricate test devices that can accurately characterize the phase evolution. The usual approaches to studying phase evolution either rely on large-scale test devices that overlook the influence of reduced device sizes or require prolonged testing that limits systematic comparisons across materials. Furthermore, modeling the phenomena at scale require simulation frameworks that can handle physics such as surface diffusion. This work aims to overcome these limitations by developing experimental and computational frameworks to study voiding and phase transformations within interconnects. To this end, test devices, termed inline microjoints, are developed for non-destructively tracking phase evolution in micro scale interconnects under thermal aging. The test devices are demonstrated on CuSn microbumps and SnBi solder joints. Results on the CuSn microbumps demonstrate that void growth in smaller sized bumps stop earlier due to the conversion of the entire solder region into Cu₆Sn₅. In the SnBi inline joints, the effective electromigration diffusivity was characterized using both thickness of Bi accumulation imaged under back scatter electron (BSE) imaging, and the rate of resistance growth. Both thickness and resistance was obtained on the same bumps due to the non-destructive nature of the test. The diffusivity values obtained were found to match closely with those reported in literature. During the interrupted testing, a nonlinear transient resistance growth was observed at the beginning of each test. The nonlinear growth could not be attributed to joule heating and the cause for it needs further investigation. </p><p dir="ltr">To complement these experimental findings, a sharp interface simulation framework based on Enriched Isogeometric Analysis (EIGA) is developed in this thesis to model intermetallic and void growth in microbumps, which aligns well with experimental outcomes. An extension to the modeling methodology is developed to simulate surface diffusion with imposed flux boundary conditions on open surfaces. The simulations are applied to model surface diffusion in Cu surface during the anneal step in hybrid bonding. The results of the simulations are shown to agree with trends reported in literature. Finally, future applications of the experimental procedure developed in this thesis in the context of hybrid bonding is also discussed. By integrating experimental and simulation techniques, this work contributes tools to analyze phase evolution in interconnects in advanced electronic packages.</p>