The counterflow pipeline concept was originated by Sproull et. al.[1] to
demonstrate the concept of asynchronous circuits. The basic premise is that a
simple architecture with only local communication and control and a simple
regular structure will result in increased performance. This thesis attempts to
analyze the performance of the basic counterflow pipeline architecture, find the
bottlenecks associated with this implementation, and attempt to illustrate the
improvements that we have made in overcoming these bottlenecks. From this
research, three distinct microarchitectures have been developed, ranging from a
synchronous version of the counterflow design suggested by Sproull to an all new
structure which supports aggressive speculation, no instruction stalling and
ultimately intrinsic multi-threading. To support high-level simulation of various
architectures a Java based simulation environment has been developed which
was used to explore the various design trade-offs and evaluate the resulting
performance of each of the architectures. / Graduation date: 1998
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/33905 |
| Date | 27 February 1998 |
| Creators | Janik, Kenneth J. |
| Contributors | Lu, Shih-Lien |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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