We propose two kinds of 1.0 Gbps LVDS ( low voltage differential signaling ) transceivers for LCD ( liquid crystal display ) in this thesis. LVDS has become a popular choice for high-speed serial links in large-sized display units. Our designs are an I/O interface circuit for Gbps operation which is fully complied with the IEEE STD 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. In the first design of the transmitter, a CMFB (common mode feedback) circuitry is utilized to stabilize the common voltage in a pre-defined range. In the second design of the transmitter, we try to use a DC bias circuitry to stabilize output common mode voltage to further improve the stability of the common mode voltage. By contrast, a regenerative circuit which provides a positive feedback loop gain between the preamplifier and the output buffer in the receiver such that the received bit streams can be correctly restored
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0726104-215721 |
| Date | 26 July 2004 |
| Creators | Huang, Jian-Ming |
| Contributors | Jih-Ching Chiu, Chua-Chin Wang, Hsiao-Hwa Chen, Ju-Ya Chen |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726104-215721 |
| Rights | restricted, Copyright information available at source archive |
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