A series of complex digital blocks have been designed and fabricated using the newly
developed current-mode differential CMOS logic family viz. the Folded Source-Coupled
Logic ( FSCL ). The main feature of this logic family is the low current spikes generated
during the switching transitions ( at least 2 orders of magnitude smaller than the
conventional static CMOS gates ). The design of a decimation filter using novel Multi-Rate
systolic architecture and it's implementation in Folded Source-Coupled Logic is also
considered. The decimation filter thus designed can be used in mixed-mode applications
like Sigma-Delta A/D converter to improve it's performance characteristics like dynamic
range, resolution and phase linearity at higher sampling rates. / Graduation date: 1992
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/37131 |
| Date | 07 May 1991 |
| Creators | Maskai, Sailesh R. |
| Contributors | Kiaei, Sayfe |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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