Since the invention of SRAM (Static Random Access Memory), many improvements have been proposed. The major targets are speed, area, and power consumption. The evolution of the CMOS process technology makes it possible to implement SRAM by using dual threshold voltage transistors. Hence, we will use TSMC (Taiwan Semiconductor Manufacturing Company) 0.25 $mu$m 1P5M CMOS process to realize the dual threshold voltage SRAM in this thesis. In order to reduce SRAM
internal power consumption, we also propose quenchers to suppress unwanted oscillation between bit lines.
In addition, several types of BIST (Build In Self Test) comparators are also proposed to test the mentioned SRAM. After detailed simulations, the proposed comparators possess impressive results in high fan-in, low transistor count, and high speed.
The proposed SRAM and BIST comparators are fabricated by the CMOS process provided by National Science Council Chip Implementation Center (CIC). The measurements of the chips are fully corrected to meet the design goals.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0924103-111412 |
| Date | 24 September 2003 |
| Creators | Lee, Po-Ming |
| Contributors | Jhing-Fa Wang, Ing-Jer Huang, Chua-Chin Wang, Bin-Da Liu, Shen-Fu Hsiao, Yau-Hwang Kuo |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0924103-111412 |
| Rights | not_available, Copyright information available at source archive |
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