While data converters have been around for nearly nighty years, mm-wave data converters
are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the
introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data
communication is the main driving force behind mm-wave data converter development.
As with any mm-wave circuit, designers must go beyond simply relying on technology
advancement to archives acceptable performance. Careful device and passive modeling is
critical and systematic design methodology may o er repeatable and scalable mm-wave
designs.
In this thesis the design methodology and architectural challenges of mm-wave ADCs
are explored. Some of the fundamental mm-wave ADC building blocks such as track
and hold ampli ers, data distribution networks and
ip-
ops are implemented in SiGe
BiCMOS and CMOS technologies and characterized. Several record breaking circuits are
presented along with systematic design methodology. The impact of these circuit blocks
on the performance of the next generation ADCs is studied and experimentally veri ed
using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/30039 |
| Date | 14 November 2011 |
| Creators | Shahramian, Shahriar |
| Contributors | Chan Carusone, Anthony, Voinigescu, Sorin |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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