In this thesis, a switched-current sample-and-hold circuit is proposed. We use feedback circuit to decrease the input impedance and to reduce the transmission error in SI cell. Furthermore, the entire memory cell is designed in a coupled differential replicate form to eliminate the clock feedthrough (CFT) error.
The sample-and-hold circuit is simulated using the parameters of TSMC 0.35£gm CMOS process. The simulation results show that the spurious-free dynamic range (SFDR) is 55 dB, the sampling rate is 40MHz, the power consumption is 0.38 mW, and the power supply is 1.5V. Furthermore, the circuit is verified by cadence-hspice simulation.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0821109-161008 |
| Date | 21 August 2009 |
| Creators | Hung, Ming-yang |
| Contributors | Tzyy-Sheng Horng, Ko-Chi Kuo, Chia-Hsiung Kao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0821109-161008 |
| Rights | not_available, Copyright information available at source archive |
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