This thesis explores the design of fast-settling pulse generators and pulsed low noise amplifiers (LNAs) for Ultra-Wideband (UWB) applications. These components are critical in pulsed UWB transceivers, and a high energy efficiency is sought without adversely affecting RF performance and functionality. To this end, new pulse generators with a subnanosecond settling time and a low energy consumption of only a few picojoules per pulse are targeted. Moreover, a novel pulsed LNA is investigated for a low power consumption that can be scaled with the duty cycle.
First, an energy-efficient tunable pulse generator is proposed for high-data-rate 3.1-10.6 GHz UWB applications. A current-starved ring oscillator is quickly switched on and off, and the amplitude envelope is shaped using a passive attenuator. The energy consumption per pulse is below 4.2 pJ while the pulse amplitude is 150 mV, yielding a high energy efficiency.
A quadrature pulse generator is then presented for 22-29 GHz UWB applications with a settling time below 0.5 ns. An inductor-capacitor (LC) oscillator is quickly switched on and off with a new technique, and the amplitude envelope is shaped using a variable passive attenuator. The energy consumption per pulse is only 6.2 pJ, and the pulse amplitude is more than 240 mV, yielding the highest energy efficiency reported to date in CMOS.
Next, a 3-10 GHz pulsed ring oscillator that offers direct quadrature phase modulation is demonstrated. Current impulses are injected into the oscillator to enable fast startup and implement quadrature phase modulation. The energy consumption and voltage swing varies from 13 pJ and 300 mV at 3 GHz to 18 pJ and 200 mV at 10 GHz respectively, yielding a high energy efficiency.
Lastly, a fast switching noise cancelling LNA is proposed for 3.1-10.6 GHz UWB applications that settles within 1.3 ns for switching speeds as high as 200 MHz. Inductive peaking is introduced in the noise cancelling topology to achieve a sub-4dB flat noise figure and a high gain of 16.6 dB for frequencies up to 10 GHz. The average power consumption is also below 10 mW with a 50% duty cycle clock. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2011-08-23 15:29:58.93
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OKQ.1974/6663 |
| Date | 23 August 2011 |
| Creators | El-Gabaly, AHMED |
| Contributors | Queen's University (Kingston, Ont.). Theses (Queen's University (Kingston, Ont.)) |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Rights | This publication is made available by the authority of the copyright owner solely for the purpose of private study and research and may not be copied or reproduced except as permitted by the copyright laws without written authority from the copyright owner. |
| Relation | Canadian theses |
Page generated in 0.0022 seconds