In this thesis, a simple vertical embedded gate (VEG) MOSFET process is proposed and demonstrated by using simulation tools of ISE TCAD and Silvaco TCAD. In fundamental electrical characteristics, we employed junctionless technology and two extra sidewall spacer gates to fabricate the Junctionless Pseudo Tri-Gate Vertical (JPTGV) MOS.
According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60 mV/dec and Ion/Ioff ~ 1010 are achieved at short gate length (Lg) 8 nm. In additional, our proposed VEG structure can also be applied for non-volatile memory. Using VEG structure to fabricate the SONOS devices have some features, it not only has three source/drain (S/D) terminals and two channels which can be operated independently, but also has two silicon nitride trap layers to provide the possible operation of multi-bit. We can apply different voltage in these three S/D terminals to achieve two bits or even four bits operation, thus the device has multi-bit characteristic is realized in this thesis.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0804111-140955 |
| Date | 04 August 2011 |
| Creators | Chang, Yu-Che |
| Contributors | Jyi-Tsong Lin, Chee-Wee Liu, Wen-Kuan Yeh, Chun-Hsing Shih, Feng-Der Chin |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804111-140955 |
| Rights | user_define, Copyright information available at source archive |
Page generated in 0.016 seconds