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The conventional floating gate NVSM will suffer some limitations for continued scaling of the device structure. Therefore, two approaches, the silicon-oxide-nitride-oxide-silicon (SONOS) and the nanocrystal nonvolatile memory devices, have been investigated to overcome the limit of the conventional floating gate NVSM. In this thesis, the SONOS-TFT with multiple nanowires structure was proposed and fabricated for memory applications. The memory characteristic of standard SONOS-TFT, channel width of the device is 1£gm, was compared with the nanowires SONOS-TFT, each channel width of the device is 65nm. The SONOS-TFT with multiple nanowires structure (NW SONOS-TFT) has good program/erase efficiency, retention and transfer characteristics due to the larger electric field at the corner region and more number of corners. The NW SONOS-TFTs can be treated as high performance devices and also as high program/erase efficiency nonvolatile memory under adequate voltage range operation. The fabrication of SONOS-TFTs with nano-wire channels is quite easy and involves no additional processes. Such a SONOS-TFT is thereby highly promising for application in the future system-on-panel display applications. In addition, the metal nanocrystals nonvolatile memory fabricated at low temperature is also studied in this thesis. The Ni-silicide nanocrystals memory was successfully fabricated at low temperature. The rapid thermal oxidation at low temperature was executed to make the metal nanocrystals aggregate. The device has superior memory characteristics, such as program/erase efficiency, retention time and endurance. The nonvolatile metal nanocrystals memory fabricated at low temperature processes is very promising for the application on the portable products and panel displays.

The conventional floating gate NVSM will suffer some limitations for continued scaling of the device structure. Therefore, the silicon-oxide-nitride-oxide-silicon (SONOS) and the nanocrystal nonvolatile memory devices, have been investigated to overcome the limit of the conventional floating gate NVSM. For driving device application, we have used multilayer ONO gate dielectrics to make change the effective dielectric constant. The proposed TFT with ONO gate dielectrics have better gate control ability. On the other hand, nanowire has larger electric-field in the corner region at the same voltage. The SONOS-TFT with multiple nanowire channels have superior electrical characteristic, such as lower threshold voltage, higher On/Off ratio, steeper subthreshold slope, and superior driving ability. The memory characteristic of standard SONOS-TFT, channel width of the device is 1£gm, was compared with the nanowires SONOS-TFT, each channel width of the device is 65nm. The SONOS-TFT with multiple nanowires structure (NW SONOS-TFT) has good program/erase efficiency, retention, transfer characteristics and can suppress gate injection effectively. These characteristics are due to the larger electric field at the corner region and more number of corners. The NW SONOS-TFTs can be treated as high performance devices and also as high program/erase efficiency nonvolatile memory under adequate voltage range operation. In this thesis, the P/E characteristics at different temperatures will also be measured and discussed. The fabrication of SONOS-TFTs with nano-wire channels is quite easy and involves no additional processes. Such a SONOS-TFT is there by highly promising for application in the future system-on-panel display applications. The SONOS-TFTs combined the TFT and memory properties at the same time. Furthermore, the process flow is compatible with conventional poly-Si TFTs fabrication without additional process steps. Hence, the application of SONOS TFTs structure can reach the goal of system on panel (SOP) in the future.

In this thesis, a simple vertical embedded gate (VEG) MOSFET process is proposed and demonstrated by using simulation tools of ISE TCAD and Silvaco TCAD. In fundamental electrical characteristics, we employed junctionless technology and two extra sidewall spacer gates to fabricate the Junctionless Pseudo Tri-Gate Vertical (JPTGV) MOS. According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60 mV/dec and Ion/Ioff ~ 1010 are achieved at short gate length (Lg) 8 nm. In additional, our proposed VEG structure can also be applied for non-volatile memory. Using VEG structure to fabricate the SONOS devices have some features, it not only has three source/drain (S/D) terminals and two channels which can be operated independently, but also has two silicon nitride trap layers to provide the possible operation of multi-bit. We can apply different voltage in these three S/D terminals to achieve two bits or even four bits operation, thus the device has multi-bit characteristic is realized in this thesis.

The increasing demands on higher density, lower cost, higher speed, better endurance and longer retention has push flash memory technology, which is predominant and the driving force of the semiconductor nonvolatile memory market in recent years, to the position facing great challenges. However, the conventional flash memory technology using continuous highly doped polysilicon as floating gate, which is the most common in today’s commercial market, can't satisfy these demands, with the transistor size continuously scaling down beyond 32 nm. Nanocrystal floating gate flash memory and SONOS-type flash memory are considered among the most promising approaches to extend scalability and performance improvement for next generation flash memory. This dissertation addresses the issues that have big effects on nanocrystal floating gate flash memory and SONOS-type flash memory performances. New device structures and new material compatible to CMOS flow are proposed and demonstrated as potential solutions for further device performance improvement. First, the effect of nanocrystal-high k dielectric interface quality on nanocrystal flash memory performance is studied. By using germanium-silicon core-shell nanocrystals or ruthenium nanocrystals buried in HfO₂ as charge storage nodes, high interface quality has been achieved, leading to promising memory device performance. Next, another crucial challenge for nanocrystal flash memory on how to deposit uniformly distributed nanocrystal matrix in good shape and size control with high density is discussed. Using protein GroEL to obtain well ordered high density nanocrystal pattern, a flash memory device with Ni nanocrystals buried in HfO₂ is demonstrated. For this technique, the nanocrystal size is restricted to the GroEL's central cavity size and the density is limited by protein template. To overcome this limitation, a novel method using self-assembled Co-SiO₂ nanocrystals as charge storage nodes is demonstrated. Separated by thin SiO₂, these nanocrystals can form close packed form to achieve ultrahigh density. Finally, charge trapping layer band engineering is proposed for SONOS-type memory for better memory performance. By manipulating the pulse ratio of Hf and Al precursor during ALD deposition, the band diagram of Hf[subscript x]Al[subscript y]O charge trapping layer is optimized to have a Hf : Al ratio 3:1 at bottom and 1:3 at the top, leading to better trade-off between programming and retention for the of memory device. / text

CloudMe is a cloud computing service used for business and home users. CloudMe facilitates the user to store their personal files like music, video, documents and images. The primary focus of this thesis is on music. The personal music files can be uploaded to CloudMe manually or by using CloudMe sync in any order just like in personal computer. CloudMe offers different services to access the cloud from other devices like smart phones, web browser and the home computer.   Sonos wireless HiFi system is a set of Sonos component interconnected with the mesh network with the primary function to play digital audio. The components include subwoofer, speakers and Bridges in order to connect to wireless speakers. Sonos system is connected to internet through Ethernet or via Wi-Fi. Sonos gives access to music libraries stored in computer, free Internet radio stations and additional music services. The controller for the complete system has various choices as iPhone, Android and other specific Sonos controllers.   However, with Sonos, a computer is considered necessary to be running all the time in order to access the personal music files from the personal computer. Combining CloudMe to Sonos allow the requirement of an always-on computer to be removed. Instead the selected personal music files can be stored with the user‟s private CloudMe account, and the music can be accessed from the cloud storage through the Internet at anytime.   The main objective of this thesis is to build the given APIs from the Sonos that are required in order to access CloudMe from Sonos. Each API handles specific task to present CloudMe through Sonos to the user. For example an API handles user authentication and another API handles the metadata accessing. All the APIs are implemented in the given server from CloudMe. This integration not only provides access roughly the way the music files are stored in the cloud, but also implemented in a way to accesses via categories like artist, albums, genre, composers and also the playlist stored in the cloud. In order to get this menu view of all the music, the metadata of the entire music library from CloudMe is accessed and programmed to differentiate music options in the menu.

No description available.

<p>This Thesis details the design, fabrication and characterization of organic semiconductor field effect transistors with silicon oxide-nitride-oxide-semiconductor (SONOS) gates for use in spiking analog neural circuits. The results are divided into two main sections. First, the SONOS structures, parallel plate capacitors and field effect transistors, were designed, fabricated and characterized. Second, these results are used to model spiking analog neural circuits. The modeling is achieved using PSPICE based software.</p> <p>The initial design work begins with an analysis of the basic SONOS structure. The existence of the ultrathin layers of the SONOS structure is confirmed with the use of Transmission Electron Microscopy (TEM) and Energy Dispersive Spectroscopy (EDS) scans of device stacks. Parallel plate capacitors were fabricated prior to complete transistors due to the significantly less processing required. The structure and behaviour of these capacitors is similar to that of the transistor gates which allows for the optimization of the structures prior to the fabrication of the transistors. These capacitors were fabricated using the semiconductor materials of; crystalline silicon, amorphous silicon, Zinc Oxide, copper phthalocyanine (CuPc) and tris 8-hydroxyquinolinato aluminium (AlQ3). These devices are then subjected to standard capacitance voltage (C-V) analysis. The results of this analysis demonstrate that the inclusion of SONOS structures in the capacitors (and transistors) result in a hysteresis which is the result of charge accumulation in the nitride layer of the SONOS structure. This effect can be utilized as an imbedded memory. Standard control devices were fabricated and analysed and no significant hysteresis effect was observed. The hysteresis effect is only observed after the SONOS devices are subject to high voltages (approximately 14 volts) which allows tunneling through a thin oxide layer into traps in the silicon nitride layer. This analysis was conducted to confirm that the SONOS structure causes the memory effect, not the existence of interface states that can be charged and discharged.</p> <p>The next step was to design and fabricate amorphous semiconductor field effect transistors with and without the SONOS structure. First FETs without the SONOS gates were fabricated using amorphous semiconductor materials; Zinc Oxide, CuPc and AlQ3 and then the devices were characterized. This initial step confirmed the functionality of these basic devices and the ability to fabricate working control samples. Next, SONOS gate TFTs were fabricated using CuPc as the semiconductor material. The characterization of these devices confirmed the ability to shift the transfer characteristics of the devices through a read and write mechanism similar to that used to shift the C-V characteristics of the parallel plate capacitors. Split gate FETs were also produced to examine the feasibility of individual transistors with multiple gates.</p> <p>The results of these characterizations were used to model spiking analog neural circuits. This modeling was carried out in four parts. First, representative transfer and output characteristics were used to replicate analog spiking neural circuits. This was carried out using standard PSPICE software with the modification of the discrete TFT device characteristics to represent the amorphous CuPc organic transistors. The results were found to be comparable to circuits using crystalline silicon transistors. Second, the SONOS structures were modeled closely matching the characterized results for charge and voltage shift. Third, a simple Hebbian learning circuit was designed and modeled, demonstrating the potential for imbedded memories. Lastly, split gate devices were modeled using the device characterizations.</p> / Doctor of Philosophy (PhD)

In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert. / In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples.

In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert. / In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples.