In this thesis, a simple vertical embedded gate (VEG) MOSFET process is proposed and demonstrated by using simulation tools of ISE TCAD and Silvaco TCAD. In fundamental electrical characteristics, we employed junctionless technology and two extra sidewall spacer gates to fabricate the Junctionless Pseudo Tri-Gate Vertical (JPTGV) MOS. According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60 mV/dec and Ion/Ioff ~ 1010 are achieved at short gate length (Lg) 8 nm. In additional, our proposed VEG structure can also be applied for non-volatile memory. Using VEG structure to fabricate the SONOS devices have some features, it not only has three source/drain (S/D) terminals and two channels which can be operated independently, but also has two silicon nitride trap layers to provide the possible operation of multi-bit. We can apply different voltage in these three S/D terminals to achieve two bits or even four bits operation, thus the device has multi-bit characteristic is realized in this thesis.

Design step for Sigma-Delta ADC is introduced. Suitable solution for performance improvement of the original Sigma-Delta ADC, which meets new requirements on resolution of 16 bits and signal bandwidth 20-50 kHz is presented. Advantage of using multi-bit quantization and DEM DWA method reducing the linearity requirements of the internal feedback DAC is shown.

The key objective of database systems is to reliably manage data, while high query throughput and low query latency are core requirements. To date, database research activities mostly concentrated on the second part. However, due to the constant shrinking of transistor feature sizes, integrated circuits become more and more unreliable and transient hardware errors in the form of multi-bit flips become more and more prominent. In a more recent study (2013), in a large high-performance cluster with around 8500 nodes, a failure rate of 40 FIT per DRAM device was measured. For their system, this means that every 10 hours there occurs a single- or multi-bit flip, which is unacceptably high for enterprise and HPC scenarios. Causes can be cosmic rays, heat, or electrical crosstalk, with the latter being exploited actively through the RowHammer attack. It was shown that memory cells are more prone to bit flips than logic gates and several surveys found multi-bit flip events in main memory modules of today's data centers. Due to the shift towards in-memory data management systems, where all business related data and query intermediate results are kept solely in fast main memory, such systems are in great danger to deliver corrupt results to their users. Hardware techniques can not be scaled to compensate the exponentially increasing error rates. In other domains, there is an increasing interest in software-based solutions to this problem, but these proposed methods come along with huge runtime and/or storage overheads. These are unacceptable for in-memory data management systems. In this thesis, we investigate how to integrate bit flip detection mechanisms into in-memory data management systems. To achieve this goal, we first build an understanding of bit flip detection techniques and select two error codes, AN codes and XOR checksums, suitable to the requirements of in-memory data management systems. The most important requirement is effectiveness of the codes to detect bit flips. We meet this goal through AN codes, which exhibit better and adaptable error detection capabilities than those found in today's hardware. The second most important goal is efficiency in terms of coding latency. We meet this by introducing a fundamental performance improvements to AN codes, and by vectorizing both chosen codes' operations. We integrate bit flip detection mechanisms into the lowest storage layer and the query processing layer in such a way that the remaining data management system and the user can stay oblivious of any error detection. This includes both base columns and pointer-heavy index structures such as the ubiquitous B-Tree. Additionally, our approach allows adaptable, on-the-fly bit flip detection during query processing, with only very little impact on query latency. AN coding allows to recode intermediate results with virtually no performance penalty. We support our claims by providing exhaustive runtime and throughput measurements throughout the whole thesis and with an end-to-end evaluation using the Star Schema Benchmark. To the best of our knowledge, we are the first to present such holistic and fast bit flip detection in a large software infrastructure such as in-memory data management systems. Finally, most of the source code fragments used to obtain the results in this thesis are open source and freely available.:1 INTRODUCTION 1.1 Contributions of this Thesis 1.2 Outline 2 PROBLEM DESCRIPTION AND RELATED WORK 2.1 Reliable Data Management on Reliable Hardware 2.2 The Shift Towards Unreliable Hardware 2.3 Hardware-Based Mitigation of Bit Flips 2.4 Data Management System Requirements 2.5 Software-Based Techniques For Handling Bit Flips 2.5.1 Operating System-Level Techniques 2.5.2 Compiler-Level Techniques 2.5.3 Application-Level Techniques 2.6 Summary and Conclusions 3 ANALYSIS OF CODING TECHNIQUES 3.1 Selection of Error Codes 3.1.1 Hamming Coding 3.1.2 XOR Checksums 3.1.3 AN Coding 3.1.4 Summary and Conclusions 3.2 Probabilities of Silent Data Corruption 3.2.1 Probabilities of Hamming Codes 3.2.2 Probabilities of XOR Checksums 3.2.3 Probabilities of AN Codes 3.2.4 Concrete Error Models 3.2.5 Summary and Conclusions 3.3 Throughput Considerations 3.3.1 Test Systems Descriptions 3.3.2 Vectorizing Hamming Coding 3.3.3 Vectorizing XOR Checksums 3.3.4 Vectorizing AN Coding 3.3.5 Summary and Conclusions 3.4 Comparison of Error Codes 3.4.1 Effectiveness 3.4.2 Efficiency 3.4.3 Runtime Adaptability 3.5 Performance Optimizations for AN Coding 3.5.1 The Modular Multiplicative Inverse 3.5.2 Faster Softening 3.5.3 Faster Error Detection 3.5.4 Comparison to Original AN Coding 3.5.5 The Multiplicative Inverse Anomaly 3.6 Summary 4 BIT FLIP DETECTING STORAGE 4.1 Column Store Architecture 4.1.1 Logical Data Types 4.1.2 Storage Model 4.1.3 Data Representation 4.1.4 Data Layout 4.1.5 Tree Index Structures 4.1.6 Summary 4.2 Hardened Data Storage 4.2.1 Hardened Physical Data Types 4.2.2 Hardened Lightweight Compression 4.2.3 Hardened Data Layout 4.2.4 UDI Operations 4.2.5 Summary and Conclusions 4.3 Hardened Tree Index Structures 4.3.1 B-Tree Verification Techniques 4.3.2 Justification For Further Techniques 4.3.3 The Error Detecting B-Tree 4.4 Summary 5 BIT FLIP DETECTING QUERY PROCESSING 5.1 Column Store Query Processing 5.2 Bit Flip Detection Opportunities 5.2.1 Early Onetime Detection 5.2.2 Late Onetime Detection 5.2.3 Continuous Detection 5.2.4 Miscellaneous Processing Aspects 5.2.5 Summary and Conclusions 5.3 Hardened Intermediate Results 5.3.1 Materialization of Hardened Intermediates 5.3.2 Hardened Bitmaps 5.4 Summary 6 END-TO-END EVALUATION 6.1 Prototype Implementation 6.1.1 AHEAD Architecture 6.1.2 Diversity of Physical Operators 6.1.3 One Concrete Operator Realization 6.1.4 Summary and Conclusions 6.2 Performance of Individual Operators 6.2.1 Selection on One Predicate 6.2.2 Selection on Two Predicates 6.2.3 Join Operators 6.2.4 Grouping and Aggregation 6.2.5 Delta Operator 6.2.6 Summary and Conclusions 6.3 Star Schema Benchmark Queries 6.3.1 Query Runtimes 6.3.2 Improvements Through Vectorization 6.3.3 Storage Overhead 6.3.4 Summary and Conclusions 6.4 Error Detecting B-Tree 6.4.1 Single Key Lookup 6.4.2 Key Value-Pair Insertion 6.5 Summary 7 SUMMARY AND CONCLUSIONS 7.1 Future Work A APPENDIX A.1 List of Golden As A.2 More on Hamming Coding A.2.1 Code examples A.2.2 Vectorization BIBLIOGRAPHY LIST OF FIGURES LIST OF TABLES LIST OF LISTINGS LIST OF ACRONYMS LIST OF SYMBOLS LIST OF DEFINITIONS

Continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADC) have emerged as the popular choice to achieve high resolution and large bandwidth due to their low cost, power efficiency, inherent anti-alias filtering and digital post processing capabilities. This work presents a detailed system-level design methodology for a low-power CT ΔΣ ADC. Design considerations and trade-offs at the system-level are presented. A novel technique to reduce the sensitivity of the proposed ADC to clock jitter-induced feedback charge variations by employing a hybrid digital-to-analog converter (DAC) based on switched-capacitor circuits is also presented. The proposed technique provides a clock jitter tolerance of up to 5ps (rms). The system is implemented using a 5th order active-RC loop filter, 9-level quantizer and DAC, achieving 74dB SNDR over 20MHz signal bandwidth, at 400MHz sampling frequency in a 1.2V, 90 nm CMOS technology. A novel technique to improve the linearity of the feedback digital-to-analog converters (DAC) in a target 11-bits resolution, 100MHz bandwidth, 2GHz sampling frequency CT ΔΣ ADC is also presented in this work. DAC linearity is improved by combining dynamic element matching and automatic background calibration to achieve up to 18dB improvement in the SNR. Transistor-level circuit implementation of the proposed technique was done in a 1.8V, 0.18μm BiCMOS process.

Stereo vision is a very useful, yet challenging technology for a wide variety of applications. One of the greatest challenges is meeting the computational demands of stereo vision applications that require real-time performance. The FPGA (Field Programmable Gate Array) is a readily-available technology that allows many stereo vision methods to be implemented while meeting the strict real-time performance requirements of some applications. Some of the best results have been obtained using non-parametric stereo correlation methods, such as the rank and census transform. Yet relatively little work has been done to study these methods or to propose new algorithms based on the same principles for improved stereo correlation accuracy or reduced resource requirements. This dissertation describes the sparse census and sparse rank transforms, which significantly reduce the cost of implementation while maintaining and in some case improving correlation accuracy. This dissertation also proposes the generalized census and generalized rank transforms, which opens up a new class of stereo vision transforms and allows the stereo system to be even more optimized, often reducing the hardware resource requirements. The proposed stereo methods are analyzed, providing both quantitative and qualitative results for comparison to existing algorithms. These results show that the computational complexity of local stereo methods can be significantly reduced while maintaining very good correlation accuracy. A hardware architecture for the implementation of the proposed algorithms is also described and the actual resource requirements for the algorithms are presented. These results confirm that dramatic reductions in hardware resource requirements can be achieved while maintaining high stereo correlation accuracy. This work proposes the multi-bit census, which provides improved pixel discrimination as compared to the census, and leads to improved correlation accuracy with some stereo configurations. A rotation-invariant census transform is also proposed and can be used in applications where image rotation is possible.

Multipath propagation and mobility in wireless communication systems give rise to variations in the amplitude and phase of the transmitted signal, commonly referred to as fading. Many wireless applications are affected by slowly varying fading, where the channel is non-ergodic, leading to non-reliable transmission during bad channel realizations. These communication scenarios are well modeled by the block-fading channel, where the reliability is quantatively characterized by the outage probability. This thesis focuses on the analysis and design of adaptive transmission schemes to improve the outage performance of both single- and multiple-antenna transmission over the block-fading channel, especially for the cases where discrete input constellations are used. Firstly, a new lower bound on the outage probability of non-adaptive transmission is proposed, providing an efficient tool for evaluating the performance of non-adaptive transmission. The lower bound, together with its asymptotic analysis, is essential for efficiently designing the adaptive transmission schemes considered in the thesis. Secondly, new power allocation rules are derived to minimize the outage probability of fixed-rate transmission over block-fading channels. Asymptotic outage analysis for the resulting schemes is performed, revealing important system design criteria. Furthermore, the thesis proposes novel suboptimal power allocation rules, which enjoy low-complexity while suffering minimal losses as compared to the optimal solution. Thus, these schemes facilitate power adaptation in low-cost devices. Thirdly, the thesis considers incremental-redundancy automatic-repeat-request (INR-ARQ) strategies, which perform adaptive transmission based on receiver feedback. In particular, the thesis concentrates on multi-bit feedback, which has been shown to yield significant gains in performance compared to conventional single-bit ARQ schemes. The thesis proposes a new information-theoretic framework for multi-bit feedback INR-ARQ, whereby the receiver feeds back a quantized version of the accumulated mutual information. Within this framework, the thesis presents an asymptotic analysis which yields the large gains in outage performance offered by multi-bit feedback. Furthermore, the thesis proposes practical design rules, which further illustrates the benefits of multi-bit feedback in INR-ARQ systems. In short, the thesis studies the outage performance of transmission over block-fading channels. Outage analysis is performed for non-adaptive and adaptive transmission. Improvements for the existing adaptive schemes are also proposed, leading to either lower complexity requirements or better outage performance. Still, further research is needed to bring the benefits offered by adaptive transmission into practical systems. / Thesis (PhD)--University of South Australia, 2010

Multipath propagation and mobility in wireless communication systems give rise to variations in the amplitude and phase of the transmitted signal, commonly referred to as fading. Many wireless applications are affected by slowly varying fading, where the channel is non-ergodic, leading to non-reliable transmission during bad channel realizations. These communication scenarios are well modeled by the block-fading channel, where the reliability is quantatively characterized by the outage probability. This thesis focuses on the analysis and design of adaptive transmission schemes to improve the outage performance of both single- and multiple-antenna transmission over the block-fading channel, especially for the cases where discrete input constellations are used. Firstly, a new lower bound on the outage probability of non-adaptive transmission is proposed, providing an efficient tool for evaluating the performance of non-adaptive transmission. The lower bound, together with its asymptotic analysis, is essential for efficiently designing the adaptive transmission schemes considered in the thesis. Secondly, new power allocation rules are derived to minimize the outage probability of fixed-rate transmission over block-fading channels. Asymptotic outage analysis for the resulting schemes is performed, revealing important system design criteria. Furthermore, the thesis proposes novel suboptimal power allocation rules, which enjoy low-complexity while suffering minimal losses as compared to the optimal solution. Thus, these schemes facilitate power adaptation in low-cost devices. Thirdly, the thesis considers incremental-redundancy automatic-repeat-request (INR-ARQ) strategies, which perform adaptive transmission based on receiver feedback. In particular, the thesis concentrates on multi-bit feedback, which has been shown to yield significant gains in performance compared to conventional single-bit ARQ schemes. The thesis proposes a new information-theoretic framework for multi-bit feedback INR-ARQ, whereby the receiver feeds back a quantized version of the accumulated mutual information. Within this framework, the thesis presents an asymptotic analysis which yields the large gains in outage performance offered by multi-bit feedback. Furthermore, the thesis proposes practical design rules, which further illustrates the benefits of multi-bit feedback in INR-ARQ systems. In short, the thesis studies the outage performance of transmission over block-fading channels. Outage analysis is performed for non-adaptive and adaptive transmission. Improvements for the existing adaptive schemes are also proposed, leading to either lower complexity requirements or better outage performance. Still, further research is needed to bring the benefits offered by adaptive transmission into practical systems. / Thesis (PhD)--University of South Australia, 2010

This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

Le sujet de cette thèse est de concevoir un prototype de capteur à pixel CMOS adapté aux couches extérieures du détecteur de vertex de l'International Linear Collider (ILC).Il est le premier prototype de capteur CMOS intégrant un ADC en bas de colonne de 4-bit et une matrice de pixels, dédié aux couches externes. L'architecture du prototype nommé MIMOSA 31 comprend une matrice de pixels de 48 colonnes par 64 lignes, des ADC en bas de colonne. Les pixels sont lus ligne par ligne en mode d'obturation roulant. Les ADCs reçoivent la sortie des pixels en parallèle achève réalisent la conversion en effectuant une approximation de multi-bit/step. Sachant que dans les couches externes de l'ILC, la densité de pixels touchés est de l'ordre de quelques pour mille, !'ADC est conçu pour fonctionner en deux modes (actifs et inactifs) afin de minimiser la consommation d'énergie. Les résultats indiquent que MIMOSA 31 répond aux performances nécessaires pour cette couche de capteurs. / This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.