Field-Programmable Gate Arrays (FPGAs) systems now comprise many processing elements
that are processors running software and hardware engines used to accelerate
specific functions. To make the programming of such a system simpler, it is easiest to
think of a shared-memory environment, much like in current multi-core processor systems.
This thesis introduces a novel, shared-memory, cache-coherent infrastructure for
heterogeneous systems implemented on FPGAs that can then form the basis of a shared-memory programming model for heterogeneous systems. With simulation results, it is shown that the cache-coherent infrastructure outperforms the infrastructure of Woods [1] with a speedup of 1.10. The thesis explores the various configurations of the cache interconnection network and the benefit of the cache-to-cache cache line data transfer with its impact on main memory access. Finally, the thesis shows the cache-coherent infrastructure has very little overhead when using its cache coherence implementation.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/25856 |
| Date | 12 January 2011 |
| Creators | Mirian, Vincent |
| Contributors | Chow, Paul |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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