• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 63
  • 25
  • 17
  • 13
  • 2
  • 2
  • 1
  • 1
  • 1
  • Tagged with
  • 143
  • 47
  • 42
  • 41
  • 41
  • 34
  • 32
  • 29
  • 26
  • 24
  • 23
  • 17
  • 15
  • 15
  • 14
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Performance Evaluation of A Multiprocessor Support for Concurrent Execution of Critical Sections

Chang, Heng-Hao 01 October 2001 (has links)
In this research, in order to improve the concurrency of critical sections on distributed shared memory multiprocessors, we designed various concurrency control support for critical sections and simulate its system performance simulation. The system features consist of:
2

Emulation of a virtual shared memory architecture

Raina, Sanjay January 1993 (has links)
No description available.
3

A multiprocessor system for real-time image generation

Serra del Molino, L. January 1987 (has links)
No description available.
4

Benchmarks for Embedded Multi-processors

Gong, Shaojie, Deng, Zhongping January 2007 (has links)
During the recent years, computer performance has increased dramatically. To measure the performance of computers, benchmarks are ideal tools. Benchmarks exist in many areas and point to different applications. For instance, in a normal PC, benchmarks can be used to test the performance of the whole system which includes the CPU, graphic card, memory system, etc. For multiprocessor systems, there also exist open source benchmark programs. In our project, we gathered information about some open benchmark programs and investigated their applicability for evaluating embedded multiprocessor systems intended for radar signal processing. During our investigation, parallel cluster systems and embedded multiprocessor systems were studied. Two benchmark programs, HPL and NAS Parallel Benchmark were identified as particularly relevant for the application field. The benchmark testing was done on a parallel cluster system which has an architecture that is similar to the architecture of embedded multiprocessor systems, used for radar signal processing.
5

Benchmarks for Embedded Multi-processors

Gong, Shaojie, Deng, Zhongping January 2007 (has links)
<p>During the recent years, computer performance has increased dramatically. To measure </p><p>the performance of computers, benchmarks are ideal tools. Benchmarks exist in many </p><p>areas and point to different applications. For instance, in a normal PC, benchmarks can be </p><p>used to test the performance of the whole system which includes the CPU, graphic card, </p><p>memory system, etc. For multiprocessor systems, there also exist open source benchmark </p><p>programs. In our project, we gathered information about some open benchmark programs </p><p>and investigated their applicability for evaluating embedded multiprocessor systems </p><p>intended for radar signal processing. During our investigation, parallel cluster systems </p><p>and embedded multiprocessor systems were studied. Two benchmark programs, HPL and </p><p>NAS Parallel Benchmark were identified as particularly relevant for the application field. </p><p>The benchmark testing was done on a parallel cluster system which has an architecture </p><p>that is similar to the architecture of embedded multiprocessor systems, used for radar </p><p>signal processing.</p>
6

General theory relating to the implementation of concurrent symbolic computation

Clarke, Thomas James Woodchurch January 1989 (has links)
No description available.
7

Communication mapping in multiprocessor platforms

Coêlho de Araújo, Cristiano January 2005 (has links)
Made available in DSpace on 2014-06-12T15:54:34Z (GMT). No. of bitstreams: 2 arquivo7168_1.pdf: 2138979 bytes, checksum: 19e8ea84018aa698112c01c9de47d857 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2005 / Os avanços na tecnologia de fabricação de circuitos integrados tem permitido a implementação de sistemas inteiros em um único chip, combinando alto poder de processamento e baixo consumo em uma pequena área. Os chamados Multiprocessor System-on-Chip (MPSoc) incluem multiplos processadores heterogeneos, estruturas complexas de interconexão e componentes de propriedade intelectual fornecidos por terceiros. Esta tecnologia permitiu o surgimento de dispositivos portateis como telefones celulares, PDAs, dispositivos multimídia que combinam a portabilidade com a capacidade de antigos computadores desktop. Contudo, a especificação e validação destes sistemas se tornou uma tarefa muito difícil. Existe um gap entre a especificação do sistema em alto nível e a implementação em uma plataforma multirprocessador. Este gap entre a especificação e a implementação não é tratado de forma adequada pelas metodologias e ferramentas existentes. Tendo como consequencia atrasos no ciclo de desenvolvimento e erros que podem comprometer o projeto. Nesta tese é atacado o problema de implementação da comunicação modelada a nível de sistema em plataformas multiprocessadores. As contribuições deste trabalho são: (1) uma nova abordagem para a modelagem de plataformas multiprocessador; (2) uma metodologia para o mapeamento de comunicação na plataforma; (3) suporte de análise para avaliação da implementação da comunicação. As metodologias e ferramentas propostas foram validadas utilizando-se dois estudos de caso. O primeiro uma aplicação com múltiplas comunicações e o segundo uma aplicação multimídia
8

A demand driven multiprocessor

Bakti, Zulkifli Abdul Kadir January 1985 (has links)
It is thought that fast low cost computers can be built by employing large numbers of cheap microprocessors working together in a system. However increasing the number of microprocessors in a parallel computer system may not produce a linear increase in performance for general purpose programming. The problems seem to lie in the communication between processors and the method of exploiting parallelism. A multiprocessor system was constructed using six MC68000 microprocessors. The problems of communication and exploiting parallelism were tackled in the design of the multiprocessor system. The component processors in a multiprocessor system communicate with each other through a communication channel. It is essential that the communication hardware has a high bandwidth. A fast communication hardware was implemented based on a two port shared memory. One method of extracting parallelism in a computing problem is by using divide and conquer. A software system was developed that enables the multiprocessor to exploit parallelism derived by the divide and conquer method. A software kernel is employed to manage the scheduling of parallel tasks to processors and the communication between processors. The mode of computation is based on the demand driven model.
9

A flexible, scalable approach to real-time graphics

Shrubsole, Paul Anthony January 2000 (has links)
No description available.
10

Energy Efficient Scheduling for Real-Time Systems

Gupta, Nikhil 2011 December 1900 (has links)
The goal of this dissertation is to extend the state of the art in real-time scheduling algorithms to achieve energy efficiency. Currently, Pfair scheduling is one of the few scheduling frameworks which can optimally schedule a periodic real-time taskset on a multiprocessor platform. Despite the theoretical optimality, there exist large concerns about efficiency and applicability of Pfair scheduling in practical situations. This dissertation studies and proposes solutions to such efficiency and applicability concerns. This dissertation also explores temperature aware energy management in the domain of real-time scheduling. The thesis of this dissertation is: the implementation efficiency of Pfair scheduling algorithms can be improved. Further, temperature awareness of a real-time system can be improved while considering variation of task execution times to reduce energy consumption. This thesis is established through research in a number of directions. First, we explore the applicability of Dynamic Voltage and Frequency Scaling (DVFS) feature in the underlying platform, within Pfair scheduled systems. We propose techniques to reduce energy consumption in Pfair scheduling by using DVFS. Next, we explore the problem of quantum size selection in Pfair scheduled system so that runtime overheads are minimized. We also propose a hardware design for a central Pfair scheduler core in a multiprocessor system to minimized the overheads and energy consumption of Pfair scheduling. Finally, we propose a temperature aware energy management scheme for tasks with varying execution times.

Page generated in 0.0385 seconds