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Konstruktion av förstärkare och insamplingssteg till en PSAADC i 0.25 um CMOS / Design of OP-amplifiers and a voltage reference network for a PSAADC in 0.25 um CMOS

The aim and goal of this work has been to design and implement a voltage reference network for a 12-bit PSAADC, Parallell Successive Analog to Digital Converter. A chip containing the design has been sent away for fabrication. Because of the long processing time, no measurement data are presented. The main specifications for the voltage reference generator is to generate stable reference voltages with low noise and a good PSRR. Efforts has also been made to minimize the power consumption.

Identiferoai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-1132
Date January 2002
CreatorsAndersson, Martin
PublisherLinköpings universitet, Institutionen för systemteknik, Institutionen för systemteknik
Source SetsDiVA Archive at Upsalla University
LanguageSwedish
Detected LanguageEnglish
TypeStudent thesis, info:eu-repo/semantics/bachelorThesis, text
Formatapplication/pdf
Rightsinfo:eu-repo/semantics/openAccess
RelationLiTH-ISY-Ex, ; 3236

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