To support the study of potential utilization of the emerging silicon carbide (SiC) devices, two SiC active switches, namely 1.2 kV, 5 A SiC JFET manufactured by SiCED, and 1.2 kV, 20 A SiC MOSFET by CREE, have been investigated systematically in this thesis. The static and switching characteristics of the two switches have firstly been characterized to get the basic device information. Specific issues in the respective characterization process have been explored and discussed. Many of the characterization procedures presented are generic, so that they can be applied to the study of any future SiC unipolar active switches.
Based on the characterization data, different modeling procedures have also been introduced for the two SiC devices. Considerations and measures about model improvement have been investigated and discussed, such as predicting the MOSFET transfer characteristics under high drain-source bias from switching waveforms. Both models have been verified by comparing simulation waveforms with the experimental results. imitations of each model have been explained as well.
In order to capture the parasitic ringing in the very fast switching transients, a modeling methodology has also been proposed considering the circuit parasitics, with which a device-package combined simulation can be conducted to reproduce the detailed switching waveforms during the commutation process. This simulation, however, is inadequate to provide deep insights into the physics behind the ringing. Therefore a parametric study has also been conducted about the influence of parasitic impedances on the device's high-speed switching behavior. The main contributors to the parasitic oscillations have been identified to be the switching loop inductance and the device output junction capacitances. The effects of different parasitic components on the device stresses, switching energies, as well as electromagnetic interference (EMI) have all been thoroughly analyzed, whose results exhibit that the parasitic ringing fundamentally does not increase the switching loss but worsens the device stresses and EMI radiation.
Based on the parametric study results, this thesis finally compares the difference of SiC JFET and MOSFET in their respective switching behavior, comes up with the concept of device switching speed limit under circuit parasitics, and establishes a general design guideline for high-speed switching circuits on device selection and layout optimization. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/30778 |
| Date | 28 January 2010 |
| Creators | Chen, Zheng |
| Contributors | Electrical and Computer Engineering, Boroyevich, Dushan, Ngo, Khai D. T., Wang, Fei Fred |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | Chen_Z_T_2009.pdf |
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