A novel CMOS inverter has been proposed. We utilize gated N-I-P transistor to
replace the conventional PMOSFET for solving the problem of width compensation.
Also, we carefully investigate and analyze the non-conventional CMOS characteristics
with NTFET and/or UTB JL MOSFET as driver and gated N-I-P transistor as a load.
According to the results, our proposed novel CMOS inverter has correct logic behavior
and its delay time is reduced about 87.2 % when compared with the CTFET. Also, our
proposed CMOS still can get a 43.2 % reduction in delay time when compared with JL
CMOS. In addition, because of the N-type output drain node and the SOI structure, our
proposed CMOS does not need any physical isolation technique, thereby improving the
packing density. Our proposed CMOS indeed obtain a 54.1 % reduction of the total area
compared with the conventional CMOS. Our proposed CMOS also can achieve a 40.1
% reduction in the total area when compared with the SOI-based CMOS. More
importantly, due to the reduced process steps, the cost reduction can be achieved. We
therefore believe that a high packing density novel CMOS inverter with reduced process
steps can become one of the contenders for future CMOS scaling.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0805111-101326 |
| Date | 05 August 2011 |
| Creators | Lu, Kuan-Yu |
| Contributors | Feng-Der Chin (Albert Chin), Jyi-Tsong Lin, Chun-Hsing Shih, Wen-Kuan Yeh, Chee-Wee Liu |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805111-101326 |
| Rights | user_define, Copyright information available at source archive |
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