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VHDL Implementation of a Fast Adder Tree

This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem. The basic research has been carried out by MATLAB programming environment and automatic generation of VHDL file based on the result obtained from MATLAB simulation. MODELSIM has been used for compilation and simulation of the VHDL file.

Identiferoai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-3838
Date January 2005
CreatorsDacheng, Chen
PublisherLinköpings universitet, Institutionen för systemteknik, Institutionen för systemteknik
Source SetsDiVA Archive at Upsalla University
LanguageEnglish
Detected LanguageEnglish
TypeStudent thesis, info:eu-repo/semantics/bachelorThesis, text
Formatapplication/pdf
Rightsinfo:eu-repo/semantics/openAccess

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