In recent years, the research focus has moved from core microarchitecture to uncore microarchitecture. Cycle-accurate models for many-core processors featuring hundreds or even thousands of cores are out of reach for simulating realistic workloads. A large portion of the simulation time is spend in the cores, and it is this portion that grows linear with every processor generation. Approximate simulation methodologies, which trade off accuracy for simulation speed, are necessary for conducting certain research. Multicore processors also demand for more advanced and rigorous simulation methodologies. Many popular methodologies designed by computer architects for simulation of single core architectures must be adapted or even rethought for simulation of multicore architectures.In this thesis, we have shown that behavioral core modeling is a competitive option for multicore studies where the research focus is in the uncore microarchitecture and considering independent tasks. We demonstrated that behavioral core models can bring speedups between one and two orders of magnitude with average CPI errors of less than 5%. We have also demonstrated that behavioral core models can help in the problem of selecting multiprogram workloads for the evaluation of multicore throughput.
| Identifer | oai:union.ndltd.org:CCSD/oai:tel.archives-ouvertes.fr:tel-00942289 |
| Date | 19 April 2013 |
| Creators | Velasquez vélez, Ricardo Andrés |
| Publisher | Université Rennes 1 |
| Source Sets | CCSD theses-EN-ligne, France |
| Language | English |
| Detected Language | English |
| Type | PhD thesis |
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