The primary focus of this thesis is to present a simple and practical implementation of an optimal-time response controller for multiphase interleaved dc-dc SMPS. This novel solution enables equal current sharing between phases not only in steady-state, but also during load transients, as well as bump-less transition between those two states. A digital voltage loop and multiple analog peak current programmed mode current loops are combined to implement a capacitor charge balance control algorithm with fairly simple hardware. This algorithm provides recovery from a disturbance in a single on-off switching action, which is performed in virtually the fastest possible time.
The hybrid interface between the loops is provided through a structure combining a sample-and-hold circuit and a relatively slow successive-approximation DAC that provides control signals for all the loops in the system. Furthermore, for operation under light load conditions, the controller automatically switches into simply implemented pulse-frequency mode of operation.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/18135 |
| Date | 14 December 2009 |
| Creators | Alico, Jurgen |
| Contributors | Prodic, Aleksandar |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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